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Clock gating is an efficient technique for reducing dynamic power in sequential circuits. It saves power by partitioning the main clock and distributing the clock to the logic blocks only when there is a need for those blocks to be activated. Synchronous circuits show reduced dynamic power dissipation for effective clock gating implementations. The paper tries to investigate different clock gating...
Adders are inevitable components in digital system design and embedded applications. The performance parameters of adders play a vital role in maximizing the efficiency of these applications. The necessity of error-tolerant circuits was prefigured in the 2003 International Technology Roadmap for Semiconductors (ITRS). Earlier works that deal with error-tolerance include flagged prefix adder and fixed...
Serial Peripheral Interface is a synchronous protocol that allows serial communication between a master and a slave device. The purpose of this paper is to provide a full description of a high speed SPI Master/Slave implementation. The designs are based on Motorola's SPI Block Guide V03.06. This paper discusses design approaches that can offer prospective ways of controlling SPI-bus, incorporating...
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