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In this paper, we show that tensor compression techniques based on randomization and partial observations are very useful for spatial audio object coding. In this application, we aim at transmitting several audio signals called objects from a coder to a decoder. A common strategy is to transmit only the downmix of the objects along some small information permitting reconstruction at the decoder. In...
An asynchronous high-performance low-power 5-port network-on-chip (NoC) router is introduced. The proposed router integrates low-latency input buffers using a circular FIFO design, and a novel end-to-end credit-based virtual channel (VC) flow control for a replicated switch architecture. This asynchronous router is then compared to an AMD synchronous router, in a realistic advanced 14nm FinFET library...
Segment Routing (SR) architecture is a promising technology. It is being standardized in collaboration between vendors and service providers. Through its simplistic control plane and the reuse of existing data planes namely MPLS and IPv6, SR helps operators to reduce the Operation Expense (OpEx) and the Capital Expense (CapEx). In the instantiation of SR over the MPLS data plane (SR-MPLS), a SR path...
Sum of Absolute Differences (SAD) is an intensive time-consuming operation of state-of-art video encoders. It is used as a block matching metric inside Motion Estimation (ME) and also on mode decision in Intra Prediction. SAD hardware architectures employ an adder tree to accumulate the coefficients from absolute difference between two video blocks. Due to the simplicity, the SAD metric is the better...
A 4F2 permanent digital archive system is presented. Data is saved by the presence of a metal nano-dot at a x-point of interconnects. This passive storage node works as a permanent memory cell with >1,000-years endurance. No transistor is used in the cell, enabling multi-layer memory stack for high-density. Mutual capacitance change due to the nano-dot presence is sensed for data retrieve. A 0/1-bit-balanced...
Stochastic computing (SC) allows for extremely low cost and low power implementations of common arithmetic operations. However inherent random fluctuation error and long latency of SC lead to the degradation of accuracy and energy efficiency when applied to convolutional neural networks (CNNs). In this paper we address the two critical problems of SC-based CNNs, by proposing a novel SC multiply algorithm...
This paper investigates the feasibility of a unified processor architecture to enable error coding flexibility and secure communication in low power Internet of Things (IoT) wireless networks. Error coding flexibility for wireless communication allows IoT applications to exploit the large tradeoff space in data rate, link distance and energy-efficiency. As a solution, we present a light-weight Galois...
Most architectures are designed to mitigate the usually undesirable phenomenon of device wearout. We take a contrarian view and harness this phenomenon to create hardware security mechanisms that resist attacks by statistically enforcing an upper bound on hardware uses, and consequently attacks. For example, let us assume that a user may log into a smartphone a maximum of 50 times a day for 5 years,...
Safety communication is very important in emerging intelligent constrained world. In order to enhance secure communication, it is essential to enhance the unreliable Constrained Application Protocol(CoAP) by adding compressed Datagram Transport Layer Security(DTLS) Protocol based on 6LoWPAN standard. The purpose of Compressed DTLS is to minimize the length of packet and to prevent from disjunction...
With the recent development in Non-Volatile Memory (NVM) technologies, several studies have suggested using them as an alternative to SRAMs in on-chip caches. However, limited endurance of NVMs is a major challenge when employed in the caches. This paper proposes a data manipulation technique, so-called Wearout Informed Pattern Elimination (WIPE), to improve the endurance of NVM-based caches by reducing...
A lot of artifiicial neural networks were proposed by scientists over the last time. Each of them can cope with the tasks of limited difficulty level, determined by their properties and capabilities. The aim of this paper is to outline difference of them and to define their positive and negative sites in different tasks of identification and control.
Cellular transport systems are a field of research which has received some attention over the last few years. As a recently established topic, a large share of the current research is directed at fundamental topics dealing with the system's design and construction. Answer set programming, on the other hand, has been established in the early 90s and received steadily rising attention from thereon....
Based on the research of ARMv4 architecture, a kind of 32bit embedded microprocessor is designed and implemented. Firstly, the ARMv4 instruction set is divided into different types according to its characteristics, which is conducive to the design of a simple structure of the decoding circuit. Secondly, an improved pipeline architecture is proposed to improve the efficiency of the instruction execution,...
This paper presents a modular architecture for dynamically reconfigurable middlebox with a customized reconfiguration handler. The data plane of this middlebox can be updated remotely at run-time by client to support post-deployment feature extension, customization and optimization. The proposed Reconfiguration Handler can achieve at least 3.19 Gbps of reconfiguration throughput, which reduces the...
We propose to learn semantic spatio-temporal embeddings for videos to support high-level video analysis. The first step of the proposed embedding employs a deep architecture consisting of two channels of convolutional neural networks (capturing appearance and local motion) followed by their corresponding Gated Recurrent Unit encoders for capturing longer-term temporal structure of the CNN features...
We present Deep Sparse-coded Network (DSN), a deep architecture based on multilayer sparse coding. It has been considered difficult to learn a useful feature hierarchy by stacking sparse coding layers in a straightforward manner. The primary reason is the modeling assumption for sparse coding that takes in a dense input and yields a sparse output vector. Applying a sparse coding layer on the output...
This paper presents a novel deep architecture for saliency prediction. Current state of the art models for saliency prediction employ Fully Convolutional networks that perform a non-linear combination of features extracted from the last convolutional layer to predict saliency maps. We propose an architecture which, instead, combines features extracted at different levels of a Convolutional Neural...
The Sum of Absolute Transformed Differences (SATD) computation is one of the most time consuming functions of the High Efficiency Video Codec (HEVC) reference model (HM). Thus, dedicated hardware architectures are demanded for such metric. In HM, the SATDs are computed using the Hadamard Transform (HT) 8×8 or 4×4. When the partition sizes are larger than those two HT sizes listed, the SATD is computed...
Multi-level Cell Spin-Transfer Torque Magnetic RAM (MLC STT-MRAM), is emerging as a promising candidate to build L2 cache. However, the high write energy impedes the adoption of MLC STT-MRAM. In this paper, we focus on reducing the write energy consumption. For a 2-bit STT-MRAM cell, the energy consumption of flipping the left bit is greater than that of flipping the right bit. Beside, writing state...
The ability of ultra-low latency to process market data feed is the premise and foundation for a today's trading system to grab the instant trading profits. The market data feed containing up-to-date information on market changes is multicasted real-timely from financial exchanges to market participants, usually in the form of financial information exchange (FIX) Adapted for STreaming (FAST) protocol...
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