The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A new high density Contact RRAM (CRRAM) cell realized in pure high-k metal gate 28nm CMOS logic process with a very small 35nm×35nm resistive contact hole has been fabricated without extra masking or process step. This study reports the first time of a manufacturable tiny resistive node of RRAM cell on a 28nm CMOS logic platform and fully compatible with high-k metal gate processes. The 28nm Contact...
A transformer based multiple coupled LC tanks model for on-chip VCO design is introduced. The merits of adoption multiple coupled LC tanks can be Q factor enhancement for the equivalent LC tank of VCO, low power consumption, better amplitude swing and broad tuning range can be obtained. As an illustration case two low power Ku band VCOs using dual LC-tanks with/without feedback designed using a 0...
This paper presents a high performance capacitive micromachined ultrasound sensor (CMUS) with a large fractional bandwidth (FB) ∼113 % and a low bias voltage of 5 V in an immersion testing of an ultrasonic sensor. The thin polysilicon for the CMOS gate was utilized as a sacrificial layer and the multiple layers of metal and dielectric for the CMOS electric interconnects were used as the structural...
This paper reports on the successful demonstration of radio frequency (RF) components in support of an integrated wide band/high dynamic range X-band receiver in 180-nm fully-depleted (FD) SOI CMOS technology. The demonstrated microwave monolithic integrated circuit (MMIC) includes an X-band low noise amplifier (LNA), Marchand balun, balanced amplifiers, double balanced mixer, non-reflective filter,...
We demonstrate an image sensor pixel with dual-layer metal grid polarizer with extinction ratio over 80 in 65-nm standard CMOS technology. By recent advanced CMOS technology, it is feasible to design sub-wavelength metal layer patterns in the visible wavelengths. Fine metal grid has high polarization characteristics. Its extinction ratio depends on the grid pitch. Thus, high extinction ratio can be...
The stacked-die packaging, one of the 3D packaging solutions, implements the vertical multi-die stacking. The technology reduces the footprint and improves packaging density effectively. In the stacked-die packaging, the dies designed with different size were connected in vertical direction by the die-attach films. The multi-layer structure is fixed on the substrate such as PCB/BT by the adhesive...
In this paper, a planar spiral inductor with defected ground structure is proposed. The single-π model is established. Equations of the self-resonate frequency and the frequency with maximum quality factor are obtained, in which explanations and approximate solutions are given. The proposed inductors were fabricated in 65nm CMOS technology. Measured results match well with simulations and models up...
This paper presents a differential 60 GHz phase shifter based on a vector modulator approach. The inclusion of a series resistor in the all-pass I/Q greatly reduces the effect of the capacitance loading change vs. bias current and results in a wideband phase shifter. The phase shifter achieves a gain of −6+/−2 dB with IP1dB of 0–3dBm at 55GHz, and an rms phase error of <11° at 40–70GHz (PDC...
Copper dual damascene BEOL technology has been in production now for 14 years and 7 CMOS generations, since it shipped in its first chips in late 1997, and was first ramped to high volume production in mid-1998. Besides benefits in performance and manufacturability, perhaps the main benefit has been to keep the door open for continued Moore's Law scaling of on-chip wiring, where Al(Cu)-based wires...
VLSI technology scaling in the 32-nm node and beyond has presented designers with increasing challenges to obtain performance gains, power and area reductions each successive generation. Maximum voltage limits, decreasing interconnect performance, and device changes have forced designers to rethink system and circuit design for enhanced system performance and improved user experience.
In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive...
Electrostatic discharge (ESD) induced failures continue to be a major reliability concern in the semiconductor industry. Such a concern will in fact be intensified as the CMOS technology is scaling toward the 22-nm and beyond. This paper covers the issues and challenges pertinent to the design of electrostatic discharge (ESD) protection solutions of modern and future integrated circuits, including...
In this paper, we demonstrate a CMOS image sensor with high extinction ratio on-chip polarizers with 65-nm standard CMOS technology. The polarizer is based on a metal wire grid fabricated with the metal wiring layers. The extinction ratio of 11.0 dB is achieved by a pixel with on-chip polarizer where the line / space widths are 90 nm / 90 nm.
This paper presents the first system-level study on the impact of carbon nanotube field-effect transistors (CNFETs) on multilevel interconnect networks. In this paper, for the first time, the gains in speed and energy-delay product (EDP) offered by CNFETs over CMOS are presented as a function of interconnect length. It is demonstrated that the respective 4.3× and 8× improvements in intrinsic delay...
A monolithic chemiresistor (CR) array micro-system with microfluidic channel for micro gas chromatograph (μGC) is presented in this paper. A CMOS readout chip was designed for amplifying and conditioning the signal of a 4×2 MPN-coated CR array fabricated on the surface of the CMOS chip. A micro glass lid with input and output capillary tubes was developed as a gas flow channel and mounted on the CMOS...
A V-band low noise amplifier has been demonstrated in 90 nm CMOS. The LNA design was used the low loss microstrip lines for all matching networks. To fulfill the metal density requirement in fabrication, the ground plane needs slots. The direction of the slot pattern affects the line loss over 30% at 60 GHz, according to the analysis and experimental results. By slot filling under the line, the line...
The design and verification of several monolithic inductor structures is presented. Based on the measurement results of proof-of-concept prototypes in 65 nm CMOS, the inductance (L) and quality factor (Q) of these structures are analyzed both qualitatively and quantitatively. Also, a closed-form approximation for the inductance of vertical spirals is presented and the results are applied to design...
This paper focuses on implementing a novel thermal switch and variable capacitance design by using commercially available CMOS MEMS process which can approach in a micro electrostatic converter system. In this system, there are two major parts. First is the variable capacitance, and the second is the thermal switch. In the variable capacitance, it implement by UMC 0.18µm one-poly seven-metal (1P7M)...
Millimeter-wave CMOS RF circuits have been received substantial attention, motivated by the advance of CMOS process [1]. In the millimetre-wave band, the connection, such as wire bonding or flip chip bonding, between the RF circuit and off-chip antenna is not easy task because of the radiation loss and/or adding parasitic components. To overcome the problem, on-chip antennas, which do not suffer from...
A three stage transformer differential cross coupled (CC) LNA and PA with integrated baluns for operation in the 57–66GHz band are presented. The LNA fabricated in a 90nm CMOS process achieves 23dB gain and 4.6dB NF at 13mA and 1.3V supply, with 0.06mm2 in size. The PA, also fabricated in a 90nm CMOS process, has maximum power added efficiency (PAE) of 19.4%, 9.4dBm Psat, and 23dB gain with a 12GHz...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.