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The growing concern in tracking, identification and localization systems has turn Radio Frequency Identification (RFID) technology into a mainstream in scientific research. In this technology, the phenomena known as the tag collision problem is becoming increasingly important, since it leads to a wastage of bandwidth, energy, and an increase in identification delay. There- fore, anti-collision protocols...
The main challenge for a design engineer is not only to design a successful SoC with a well-structured and synthesizable RTL code but also to design it with efficient in energy and optimized in power consumption. The aim of the paper is to implement AMBA APB (advanced microcontroller bus architecture — advanced peripheral bus) Bridge with efficient deployment of system resources. For this, simulation...
In this paper, a 6-bit 320-MS/s successive approximation register analog-to-digital converter (SAR ADC) is presented. The 2-bit/cycle technique and tri-level based charge redistribution technique are utilized to achieve high conversion rate and reduce the hardware cost. The proposed ADC is designed and implemented in a 65-nm CMOS process. Simulation results show that it accomplishes 48.52-dB SFDR,...
In today's VLSI world, the designers concentrate on low power design, neglecting the test methodology. Defining low power test methodology is the need of the day. In this paper, Microcode based Asynchronous P-MBIST is implemented, measured and compared with similar feature Synchronous PMBIST. The implemented core has given Power, Area advantage of 95.44%, 23.95% respectively but with increased Timing...
Low-power digital interfaces are a crucial component of reconfigurable systems. We have designed a SPI-compatible, four-wire interface and state machine for use in dynamically scaled voltage systems. The interface features an activity enable signal and latch enable signal on every eighth-bit in order to minimize the total switching power consumed by the interface. The interface also allows for addressing...
The rapid raise of embedded systems design complexity and size has emphasized the importance of high-performance simulation models. This has resulted in emergence of design methodologies at the higher levels of abstraction such as Electronic System Level (ESL) and Transaction Level Modelling (TLM) and SystemC language as the main instrument. In practice, system architects and system integrators often...
This paper presents some of the issues of signal and power integrity in relation with appropriate modeling and simulation methods that are available. The clock signal of a communication protocol is experimentally tested in order to find the rules to improve its signal integrity (SI) along the paths on the printed circuit board (PCB). The signal and power integrity of this PCB are improved using a...
There is renewed interest in the use of non-Foster circuit elements in a variety of important applications such as wideband impedance matching and artificial magnetic conductors. Although non-Foster devices such as negative capacitors and negative inductors can be realized using current conveyors and Linvill circuits, a digital design approach may offer an important alternative in some applications...
A novel level-up shifter with dual supply voltage is proposed. The proposed design significantly reduces the short circuit current in conventional cross-coupled topology, improving the transient power consumption. Compared with the bootstrapping technique, the proposed circuit consumes significantly less area, making it more practical for ICs with a large number of supply voltages. The minimum power-delay...
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 25% reduction of power consumption is achieved by the proposed unit. In the 32/33...
We investigate the impact of single-event upsets in dynamic flip-flop circuits, which are more appealing for the design of high-performance microprocessors because of short latency, small area and high clock frequency. Previous work either uses the approaches for static flip-flops to evaluate SEU effects in dynamic flip-flops or overlook the SEU injected during the precharge phase. We re-examine the...
This paper presents a phase independent 66:8 gearbox design for 100GE PCS TX system, compatible with IEEE P802.3ba standard. By using a kind of phase independent architecture, the gearbox can convert data width from 66-bit to 8-bit stably. In addition, architecture optimization and pipeline technique are also applied to increase the working speed of the gearbox circuit. The optimized PCS TX circuit...
Quantum-dot Cellular Automata (QCA) is an emerging technology for nano-scale computing. There is an ever increasing demand for reliable data transmission over telecommunication networking systems. The researchers are focusing on developing nano-devices that can detect/check errors during information communication. In this paper novel 3-bit odd- and even-parity generators and checkers using QCA nanotechnology,...
Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to reduce size as well as power consumption of switching devices for Very Large Integrated Circuits (VLSI). Moreover QCA circuits offer an advantage of very high device density, high speed, high fan out, and lower circuit complexity. The QCA based circuits have been used for implementations of basic logic gates like AND, OR, NOT as...
Co-design and co-verification of complex SoC requires a virtual platform, which in an ideal case has the single source codes with hardware blocks included. An effective way to do that is using the SystemC language together with high level synthesis technology. Execution of the virtual platform requires simulation of SystemC parts, which is quite time-consuming. We present an approach to accelerate...
This paper proposes a novel low-power burst-mode clock recovery circuit (CRC) based on analog phase interpolator (PI). Accordingly, we employed a new configuration for PI-based CRC in which a novel architecture is utilized for double-edge triggered sample-and-hold (DT-SH). In the proposed DT-SH one buffer is shared between two single-edge triggered SH (ST-SH) resulting in great reduction of total...
Multipliers are considered to be an important component in DSP applications like filters. Designing high-speed multipliers with low power have substantial research interest. Modified Booth Multiprecision Multiplier (MBMP) reduces the power consumption by selecting the small precision multipliers in accordance with the selection of input operands selector. The large area overhead can be reduced by...
With the increase in wireless communication technology, encryption of information sent has become a major concern. This involves both the software level and hardware level encryption. GSM was the first cellular system that paid attention to secure mobile communication. Before the advent of GSM the cellular system had no particular security. The GSM voice calls are encrypted using a family of algorithms...
In this paper, we study the global clock synchronization and ranging problem for wireless sensor networks in the presence of unknown exponential delays using the two-way message exchange mechanism. Based on the Alternating Direction Method of Multipliers (ADMM), we propose a fully-distributed synchronization and ranging algorithm which has low communication overhead and computation cost. Simulation...
This paper proposes a new compensation technique to reduce the clock jitter effects for the continuous-time sigma-delta (CT-ΣΔ) modulator by using divided-by-n (D-N) feedback DAC waveform. There are two types of clock jitter: independent clock jitter (random jitter) and accumulated clock jitter (deterministic jitter). This technique provides a useful approach to solve one of the critical non-idealities,...
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