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The high-speed camera is an imaging device that records a particular transient state or all of the high-speed processes. It can accurately record the transient process of the high-speed target in real time and thus allow us to achieve the purpose of analysis of high-speed process through the slow motion playback. So the high-speed camera becomes an important tool for the study of the transient phenomena...
This paper presents an efficient design method used to implement high performance multi-mode memory controllers which fits different applications with different demands. The proposed design method is based on the use of dynamic partial reconfiguration (DPR) to commute from mode to another using time-multiplexing on the same chip region to save considerable area and enable usage of low-cost FPGAs....
In the dataflow computation model, instructions or tasks are fired according to their data dependencies, instead of following program order, thus allowing natural parallelism exploitation. Dataflow has been used, in different flavors and abstraction levels (from processors to runtime libraries), as an interesting alternative for harnessing the potential of modern computing systems. Sucuri is a dataflow...
Multi-operand addition is found in many real-life applications. Field Programmed Gate Array (FPGA) has emerged as a platform for realizing digital systems. In this paper, we propose an approach for realizing multi-operand addition using ternary-adders on FPGAs. We focus on the case where the operands are of different sizes. The proposed approach reduces the area of the final implementation while reducing...
This paper describes a distributed wireless acoustic sensor network (WASN) platform called WHISPER that is capable of synchronous multichannel sampling at different spatial locations with a sampling clock whose relative jitter is less than 300 ns. The platform comprises up to four data acquisition modules with onboard computing capabilities, and that can form an ad-hoc Wi-Fi network allowing an additional...
The problem of scalable and optimal behavior-style description of the binary encoder implementation into FPGA was examined. The structural synthesis technique of the binary encoder with input requests filtration and error detection circuits, which allow improving FPGA resource utilization in comparison with typical description, was proposed. The results of research and development, which have presented...
The Keyed-Hash Message Authentication Codes(HMAC) is a useful mechanism for message authentication. In this paper, a high-performance HMAC/SHA-3 processor which can generate HMAC message digest and hash message digest is presented. Not only the standard length (224,256,384,512) of the message digest can be generated, but also a length of 64-bit message digest. Due to the application of new generation...
Recently, a new lightweight block cipher, SKINNY, has been proposed by Beierle et al. in Annual Cryptology Conference 2016. This paper presents an area-efficient FPGA implementation of SKINNY block cipher. In this paper, a new column-serial structure is proposed to speed up SKINNY without compromising its area cost, and the implementation of SKINNY S-box is optimized by utilizing FPGA embedded dual-port...
Annotation — This paper presents a synthesis method for delay time evaluation in the printed circuit boards based on Timed Hard Petri Nets. For the specification and modeling of the delay time evaluation system, Timed Synchronous Petri Nets (TSPN) are used. The transition to the hardware description of the system is achieved by translating the TSPN into Timed Hard Petri Net (THPN). The implementation...
A system-on-chip field gate programmable array (FPGA)-based video processing platform for human detection in complex scenes is presented. This study details the hardwarebased implementation of a human detection algorithm in 2D/3D scenes, including the capture, video processing, and display stages. The proposed method is implemented by extending a previously proposed method that uses features extracted...
This study proposes a system-on-a-chip, field-programmable gate array (FPGA)-based real-time video processing platform for human action recognition. We provide the details of a hardware implementation for real-time human activity recognition in 3D scenes, including capture, processing, and display. The proposed platform is implemented by adding a two-stage preprocessing step to improve the results...
For the miniaturization of two-dimensional autocollimator, a method of using embedded measurement system instead of special host computer is presented. This system integrates CMOS image sensor's driving circuit, frame processing, adaptive exposure control, centroid subdivision and localization of cross, misalignment angle calculation, display driver and other functions within a FPGA chip, and the...
We present an energy efficient QRS detector for real-time ECG signal processing implemented in ASIC. An adaptive thresholding scheme based on forward search interval (FSI) algorithm together with simple preprocessing is proposed to accurately detect QRS peaks. The Verilog HDL codes with improved hardware utilization efficiency are validated using FPGA, achieving 99.59% sensitivity (Se) and 99.63%...
The data transmission is fairly quick and easy in recent years. Nowadays, there are many serial data transmission methods, such as I2C, SPI, RS-232, USB (Universal Serial Bus), and so on. Recently, USB not only works with convenience but also transmits data fast. It becomes a standard peripheral interface between FPGA development board and personal computer (PC). To satisfy those requirements, the...
A real-time hardware architecture based on scale-invariant feature transform algorithm (SIFT) feature extraction with parallel technology has been introduced in this paper. The proposed parallel hardware architecture could be able to extract feature via a Field-Programmable Gate Array (FPGA) chip efficiently, which provided the real-time performance and the similar accuracy with software implementation...
We have proposed synchronized Spread-Spectrum Code-Division Multiple-Access (SS-CDMA) communication for location and short message communication system using Quasi-Zenith Satellite System (QZSS) as a safety confirmation system at the time of grade disaster. In this communication, the satellite reception timings of all uplink signals are synchronized using transmission timing control method in order...
In this paper, a vehicle adaptive cruise control (ACC) hardware in-the-loop (HIL) platform is established to test different control strategies. This platform consists of the longitudinal vehicle dynamic model established in LabVIEW and the controller designed by the field-programmable gate array (FPGA). Due to the complex control algorithm of ACC system, FPGA with the ability of high-speed calculation...
In this paper, loss equivalent models of power electronic elements are built to discuss the power loss and efficiency of power electronic systems in real-time simulation. Based on element's dynamic characteristic and loss theory, loss equivalent models which include power switch, inductor and capacitor are established. A real-time simulation circuit of boost converter is tested and compared with the...
Due to technology scaling, which means smaller transistor, lower voltage and more aggressive clock frequency, VLSI devices are becoming more susceptible against soft errors. Especially for those devices deployed in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena...
This paper describes circuit techniques for high speed transceivers used in FPGA applications. Three architectures in 16nm FinFET encompassing NRZ and PAM4 modulation are discussed. First, a 0.5–32.75Gb/s flexible reach NRZ transceiver achieves BER <10−15 over 30dB loss backplane at 32.75Gb/s while consuming 577mW. It features 3 stages of CTLE including a gain segmented AGC, 15 tap DFE, 2 LC PLLs...
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