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Thermal design of electric machines frequently involves tests on a fully constructed prototype to calibrate various build factors associated with the manufacture, assembly and materials used in the hardware construction. The prototype machine is usually instrumented with multiple temperature sensors providing a detailed insight into the temperature distribution. The resolution of the experimentally...
The Design Security Rule Check (DSeRC) framework is a first step toward automating the analysis of integrated circuit design vulnerabilities. By mathematically modeling vulnerabilities at each abstraction level and associating them with metrics and rules, DSeRC aims to help designers quantitatively assess potential problems early on, improving security and reducing design costs.
Hardware Trojan (HT) is an intentional and the undesired modification of the integrated circuit (IC) and major security issue for the semiconductor industry. HT alters the normal working of IC, can leak the secret information or may damage the IC permanently. Due to the small size of the devices on IC, detection of trojan is very difficult by normal testing methods. In this paper, a side channel based...
The globalization of Integrated Circuits (ICs) supply chain has raised security concerns on how to ensure the integrity and the trustworthiness of fabricated circuits. While existing attack and protection methods are developed for CMOS based circuits, the introduction of emerging transistors acts as a double-sided sword. The usage of emerging devices introduces new security issues which the attackers...
Technology scaling along with unprecedented levels of device integration has led to increasing numbers of analog/mixed-signal/RF design bugs escaping into silicon. Such bugs are manifested under specific system-on-chip (SoC) operating conditions and their effects are difficult to predict a-priori. This paper describes recent advances in detecting and diagnosing such bugs using "guided" stochastic...
Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using...
The microcircuit industry is witnessing a massive outsourcing of the fabrication of ICs (Integrated Circuit), as well as the use of third party IP (Intellectual Property) and COTS (Commercial Off-The-Shelf) tools during IC design. These issues raise new security challenges and threats. In particular, it brings up multiple opportunities for the insertion of malicious logic, commonly referred to as...
Scalability is a key challenge for digital spiking neural networks (SNN) in hardware. This paper proposes an efficient neuron architecture (ENA) to reduce the silicon area occupied by neurons. As the computation resource (e.g. DSP in FPGAs) is limited for hardware SNNs, the proposed ENA employs a sharing mechanism of computing component at two levels (synapse and neuron) to reduce the occupied resources...
Real-time simulation technique of power systems is becoming realizable due to the growing significant computational power of computing platform. This paper builds a real-time prototypical platform based on PXI and LabVIEW as its main hardware and software architecture. Taking advantage of the integration characteristics of NI products, the platform embodies high expansibility and good compatibility...
The top-down approach to system design allows obtaining separate specifications for each subsystem. In the case of vision systems, this means propagating system-level specifications down to particular specifications for e. g. the image sensor, the image processor, etc. This permits to adopt different design strategies for each one of them, as long as they meet their own specifications. This approach...
The fault injection technique is utilized for simulation-based verification of safety-related analog and mixed-signal (AMS) circuits for compliance with safety requirements in the presence of hardware faults. Exhaustive fault simulation is very time consuming with respect to the number of faults to simulate at circuit level. For efficient simulation-based verification, a fault grouping approach is...
Recently, a passive device — memristor has received wide attention in nano-scale design due to its applications in the area of nanoelectronic memory design, neuromorphic computing and logic design. This passive element is non-volatile in nature and has dual properties of memory and resistor. In recent time, the application of this device in designing high speed logic circuits has now opened a new...
Hardware Trojans can be inserted by an adversary at any phase of IC manufacturing. In this paper, a methodology is proposed to detect Trojans inserted after design sign-off i.e the Trojan insertion occurs at layout level. In such attack models, golden IC are not always available in all cases, thus requiring golden IC free detection methodologies. This work exploits the concept of symmetric path delays...
A key feature of autonomous systems is the ability to solve computationally intensive tasks while adapting to changes in the environment. The learning capabilities required for this feature are underdeveloped in artificial systems, especially when compared to those of humans and animals. We aim at the implementation of biologically inspired learning algorithms to be embedded in full-custom VLSI spiking...
In this paper an analog cellular neural network is proposed with application in physical unclonable function design. Dynamical behavior of the circuit and its high sensitivity to the process variation can be exploited in a challenge-response security system. The proposed circuit can be used as unclonable core module in the secure systems for applications such as device identification/authentication...
Inexact circuits and approximate computing have been gaining a lot of interest in order to improve performances and energy efficiency beyond the boundaries of conventional digital circuits. Image and video processing is one of the best candidate for applying such techniques. As one of the key building blocks, Discrete Cosine Transform (DCT) accelerators are investigated using pruned arithmetic circuits...
While the move to smaller transistors has been a boon for performance it has dramatically increased the cost to fabricate chips using those smaller transistors. This forces the vast majority of chip design companies to trust a third party -- often overseas -- to fabricate their design. To guard against shipping chips with errors (intentional or otherwise) chip design companies rely on post-fabrication...
Abstracting word information from gate-level designs is essential for formal verification, technology mapping and hardware security applications. In this paper, we present a novel method to abstract the word-level information from arithmetic gate-level circuits using a computer algebraic approach. The proposed technique translates the gate-level circuit into algebraic domain and applies algebraic...
Globalization trends in integrated circuit (IC) design using deep submicron (DSM) technologies are leading to increased vulnerability of ICs against malicious intrusions. These malicious intrusions are referred as hardware Trojans. One way to address this threat is to utilize unique electrical signatures of ICs. However, this technique requires analyzing extensive sensor data to detect the intruded...
The development of circuit testing and verification methods is commonly driven by formal analysis centered on an abstract mathematical model of the error or defect the method is designed to detect. Hardware Trojans, however, confound attempts to develop simple representative models due to the varieties of their physical embodiments in a circuit and the creative nature of a rational human adversary...
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