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A low-power high linearity CMOS Gm-C channel select filter for WLAN/WiMax receivers in 90-nm CMOS technology is presented. To reduce power consumption a biquad cell with simple architecture and few devices is used. A simple but efficient technique is also used to improve the linearity of the filter without increasing its power consumption. The cutoff frequency of the sixth order Butterworth low-pass...
A 5.2 GHz CMOS LC voltage-controlled oscillator (VCO) for UWB receiver, fabricated using CMOS 0.18μm process, is presented in this paper. The tuning range of the proposed VCO is mainly broadened by novel negative resistance and tapping inductance techniques. Measured results of the proposed VCO reveal phase noise of -116.708/Hz at 1 MHz offset and tuning range of 4.567GHz~5.832GHz (24.32%) while consuming...
In this work a highly integrated, ultra-low-power BPSK receiver for short-range wireless communications is presented. The receiver consists of a power divider, two injection-locked RC oscillators with limiting buffers and an XOR output stage. The demodulation principle is based on the dynamic phase response of the two BPSK signal injected oscillators. As proof of concept, a 300 MHz receiver was implemented...
This paper presents a digital-intensive RF sampling receiver composed of a noise-canceling bandpass low-noise amplifier (LNA) and an RF analog-to-digital converter (ADC) for multi-band multi-mode wireless communication. The proposed LNA employs an on-chip transformer to combine the outputs of a common-gate and a common-source LNA to reduce the noise figure and enhance the linearity, while providing...
A dual-band RF receiver front-end for DVB-H is presented in this paper. It includes two sets of single-ended input LNAs, respectively followed by a double-balanced current-driven passive mixer with a low impedance load. The receiver front-end is implemented in a 1P6M 65 nm CMOS process and occupies a total chip area of 2.17 mm2. It exhibits a conversion gain of 36.5 dB, an IIP3 of -13.1 dBm, an IIP2...
A receiver front-end for an Ultra-Wide-Band system in 33.6-5-GHz band is reported. An on-chip balun is implemented in between the low noise amplifier and the mixer, which makes the input matching less stringent as compared to the structure of putting the on-chip balun prior to the LNA. Consequently, the low noise amplifier can be single-ended, resulting in low power and low area; while the differential...
This contribution deals with the novel conception of design approach to RF wideband and multiband receivers. New methodology of spatial sampling and spatial sampling method of standing wave is presented. Front-end RFIC receiver, utilizing spatial sampling method of standing wave for down converting to baseband and demodulation, has been proposed and analyzed. The whole system is proposed to be implemented...
This paper presents a low power super-regenerative Impulse-FM-UWB transceiver architecture for wireless body area networks. The design architecture consists of two different colpitts oscillators tuned at 3.5GHz and 4GHz. The external PCB loop antenna is incorporated into these oscillators as an inductive element to achieve high sensitivity and selectivity. These oscillators transmit impulses of FM-UWB...
This paper presents a design of a 3rd order Butterworth Gm-C Low Pass Filter (LPF) for WiMAX receivers in a 90 nm CMOS process. Due to its robustness to process parameter tolerances, a passive LC-ladder filter was emulated using the Signal Flow Graph (SFG) method. As a building block for the LPF, a highly linear operational transconductance amplifier (OTA) based on bias-offset cross-coupled differential...
A digital baseband receiver ASIC that supports GSM/GPRS/EDGE and Evolved EDGE is implemented in 0.13 ??m CMOS technology. The design centers around two main blocks: an adaptive channel equalizer processes GMSK/8PSK/16QAM and 32 QAM modulated signals and a flexible channel decoder supports convolutional and turbo codes, as required for Evolved EDGE. The receiver occupies 2.0 mm2 and the average power...
A programmable analog baseband beamformer for a 4-antenna 60 GHz phased-array receiver is implemented in 40 nm digital CMOS. It is based on current amplifiers employing shunt feedback. The phase shifter resolution is better than 20??, with a bandwidth of 1.7 GHz, power consumption of 35 mW, input-referred noise current of 170 nArms and output IP3 of -6 dBV.
A 900 MHz direct-conversion receiver with a ΔΣ feedback loop to RF occupies an active area of 1.2 mm2 in 65 nm CMOS. The concept prototype for low-band cellular operations achieves NF of 2.3 and 6.2 dB in conventional and ΔΣ modes, respectively, and out-of-band IIP3 up to ±4 dBm when the ΔΣ loop is active. The chip consumes 80 mW from a 1.2 V supply.
A 65 nm CMOS 2.4 GHz wake-up receiver operating with low-accuracy frequency references has been realized. Robustness to frequency inaccuracy is achieved by employing non-coherent energy detection, broadband-IF heterodyne architecture and impulse-radio modulation. The radio dissipates 415 ??W at 500 kb/s and achieves a sensitivity of -82 dBm with an energy efficiency of 830 pJ/bit.
The clock path in a 65 nm CMOS receiver comprises two injection-locked oscillators to frequency-multiply, deskew, and track correlated jitter on a pulsed clock forwarded from the transmitter. Latency mismatch and data rates are accommodated by controlling jitter tracking up to 300 MHz. Each receiver consumes 0.92 pJ/b at 7.4 Gb/s with a jitter tolerance of 1.5UI at 200 MHz.
An envelope detector-based wake-up receiver front-end is presented. A double-sampling technique is implemented to suppress the 1/f noise and DC offset, resulting in a lower output noise level and therefore a better SNR for a given input level. The receiver consumes 51 μW and occupies 0.36 mm2 in 90 nm CMOS. For 10 kb/s 00K reception it achieves -69 dBm and -80 dBm sensitivity at 2.4 GHz and 915 MHz...
A 65 nm CMOS multistandard multiband mobile broadcasting receiver SoC that covers DAB/T-DMB, ISDB-T 1seg and FM is introduced. The SoC consists of RF/AFE, power management and demodulator. The power consumption is 35 mW with a die size of 2.9??2.9 mm2. The RF/AFE area is 2.3 mm2. The sensitivities are -103 dBm, -98 dBm, and 1 dBuV for T-DMB, 1 seg and FM, respectively.
A 2.5 mm2 GPS radio chip with a robust interference rejection performance working in the L1 band at 1575.42 MHz is implemented in a 65 nm CMOS process. The receiver with internal LNA shows 2.3 dB NF, 30 dB IRR, and -15 dBm blocker IP1dB at 1710 MHz. Power consumption of 23 mW from a single 1.8 V supply is achieved by using a switched-mode power supply (SMPS).
A single-chip RF receiver to support EDGE Evolution with downlink dual-carrier (DLDC) receive diversity and EVM < 3% in all bands for demodulating 32-QAM signals is described. DLDC multistat class 39 and single-carrier multistat class 44 have been achieved. Both receive paths achieve a l\IF < 2.5 dB, an IIP3 >-3.5 dBm in the GSM 850/900 MHz band, and each draws < 57 mA from battery.
A Multi-band CMOS front-end was designed and fabricated in a 0.13μm CMOS process. The front-end employs a common-gate low noise amplifier (LNA) with capacitive cross coupling (CCC) technique and a double balanced mixer. The band selection is performed by switching capacitors in and out of the LNA load, changing the resonance frequencies ranging from 2.5GHz to 4.5GHz in 16 different frequency bands...
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