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This paper presents a novel reconfigurable circuit capable of implementing the entire family of 4-phase latch protocols. The architecture utilizes look-up-table based reconfigurable logic structures and fixed signal paths. The implemented circuit creates a fabric to realize a variety of high speed and low power controllers for asynchronous circuits on FPGAs. The circuit is implemented on the IBM Artisan...
In recent years, the RapidSmith CAD tool [1] has been used with ISE to create custom CAD tools targeting Xilinx FPGAs. This tool flow was based on the Xilinx Design Language (XDL), a human-readable representation of a netlist that contains placement and routing information. The XDL interface also provided device representation files (XDLRC files), detailing the available resources of a given FPGA...
Continuous shrinking of transistor size to provide high computation capability along with low power consumption has been accompanied by reliability degradations due to e.g., aging phenomenon. In this regard, with huge number of configuration bits, Field-Programmable Gate Arrays (FPGAs) are more susceptible to aging since aging not only degrades the performance, it may additionally result in corrupting...
This paper presents enhancements to the Xilinx UltraScale+ clocking architecture to support fine-grain time-borrowing. Time borrowing improves performance by redistributing timing slack between fast and slow paths. The Ultra-Scale+ architecture introduces programmable hardware delays and pulse generators embedded in the clocking tree to support time-borrowing based both on clock skew scheduling and...
The emergence of 2.5D and 3D packaging technologies enables the integration of FPGA dice into more complex systems. Both heterogeneous manycore designs, which include an FPGA layer, and interposer-based multi-FPGA systems support the inclusion of reconfigurable hardware in 3D-stacked integrated circuits. In these architectures, the communication between FPGA dice or between FPGA and fixed-function...
Routing of nets is one of the most time-consuming steps in the FPGA design flow. While existing works have described ways of accelerating the process through parallelization, they are not scalable. In this paper, we propose ParaFRo, a two-phase hybrid parallel FPGA router using fine-grained synchronization and partitioning. The first phase of the router aims to exploit the maximum parallelism available...
The rapid shrinking of the feature size in CMOS technology has significantly increased the power density of integrated circuits, leading to excessive temperature. Though online thermal management techniques such as DVFS and task migration can mitigate the temperature issue, but usually incur significant performance penalty. Therefore, it is crucial to optimize temperature at the design stage. In this...
This paper introduces cycle-reconfigurable modules that enhance FPGA architectures with efficient support for dynamic data accesses: data accesses with accessed data size and location known only at runtime. The proposed module adopts new reconfiguration strategies based on dynamic FIFOs, dynamic caches, and dynamic shared memories to significantly reduce configuration generation and routing complexity...
The rapid growth of wire RC delay with technology scaling has put increasing pressure on FPGA architects to make more efficient use of the different layers available in the metal stack. While commercial FPGA architectures have implemented the majority of inter-logic-block wiring on the lower metal layers and a small fraction of wires on the least-resistive upper metal layers, published explorations...
We can embed the crossbar functionality of NoC (network-on-chip) routers onto the hard multiplexers of Xilinx DSP48E primitives to support resource efficient mapping of FPGA overlay NoCs. This embedding also permits the use of dedicated hard wiring resources of the DSP cascade links to support vertical NoC channels. This unique mapping allows us to significantly reduce soft logic (LUTs+FFs) utilization...
Current trends in front end radar processing have dynamically evolved with the rapid development and integration of Field Programmable Gate Array (FPGA) technologies meriting high speed digital data processing (DSP) capabilities. The meritocracy of FPGAs depends on Fast real time Impulse Response (FIR) filtering algorithms and applications added in the rapid adoption and integration of FPGAs for Radio...
The SRAM cells that form the configuration memory of an SRAM-based FPGA make such FPGAs particularly vulnerable to soft errors. A soft error occurs when ionizing radiation corrupts the data stored in a circuit. The error persists until new data is written. Soft errors have long been recognized as a potential problem as radiation can come from a variety of sources. This paper presents an FPGA fault...
In this paper, a configurable ring oscillator PUFs (c-ROPUFs) is utilized to improve PUF entropy and reliability. In addition, a novel security technique to enhance PUF's reproducibility using a newly defined parameter namely intra-die diverseness is introduced. An implementation of c-ROPUF on a Xilinx Spartan-3E FPGA on 30 different chips under different environmental conditions is shown. Experimental...
For decades computer architects pursued one primary goal: performance. Transistor scaling has translated into remarkable gains in operating frequency and reduction in power consumption. However, increased complexity from the device to architecture levels impose several new challenges, including a decrease in dependability/reliability due to physical failures. Reconfigurable platforms are highly susceptible...
FPGA-based time-to-digital converters provide a relatively low cost and flexible solution to test and measurement applications. However, the choice of time-to-digital conversion techniques is limited by the FPGA architecture, and the measurement resolution and accuracy suffer from inevitable intra-FPGA variations. In this paper, we propose a multi-channel time-todigital conversion technique. The basic...
This paper proposes a dual-clock based solution for QC-LDPC partially parallel flooded decoders. It aims at reducing memory and routing overhead, while maintaining a high degree of parallelism at processing node level. We take advantage of the high memory working frequencies with respect to the processing units, and use two clock domains: a high frequency for memory and the barrel shifter based routing...
Field-programmable gate arrays (FPGAs) are used in various systems that use reconfigurable function. Conventional FPGAs have been developed by a transistor-level description for minimizing routing delay. Although FPGAs developed by the register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the...
A major obstacle to the uptake of advanced fabrication nodes by small industry is high NRE costs, mainly due to initial mask generation. The Programmable Structured ASIC (psASIC) is intended to bridge the gap between FPGA and Structured ASIC approaches to application design. The psASIC prototype environment comprises a pair of stacked chips, one containing only logic and the other comprising only...
NoC has a significant impact on the power, area and performance of multi-core architectures. The contribution of NoC in the total power budget of a CMP is approximately 30 to 40% [1], and the input buffers of router consume most of it. Therefore, the designers need to design a low power communication architecture of NoC by reducing the power consumption of buffers. In the existing techniques, virtual...
Ensuring security without compromising the efficiency and flexibility of a system is fundamentally a very challenging task for Researchers and Practitioners. One of the fundamental requirements is to execute security algorithms in isolation but with rest of the applications running in any high assurance system. Typically, this requirement is realized by physical separation achieved using a separate...
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