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This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of 32-bit RISC processor and a clock gating algorithm using ODC (observability don't care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB (branch target buffer) and 4-way set associative cache using pseudo LRU (least recently used) algorithm...
Field programmable gate arrays (FPGAs) become very popular for embedded cryptographic operations. In order to resist side-channel attacks, FPGAs must implement reasoned countermeasures. The most efficient way to mitigate attacks is to adopt a gate-level protection. Two secure gates families exist: those that ldquohiderdquo and those that ldquomaskrdquo side-channel leakage. In this article, we detail...
This paper presents the design and implementation of BORPHpsilas kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics resembling that of conventional UNIX file I/Os, an FPGA accesses the file system through a special hardware system call interface. By extending the semantics of a UNIX pipe, a single file system access mechanism is used for...
Field-programmable gate arrays provide a flexible and easy-to-configure implementation platform that supports the development of tamper-proof networked embedded systems. Many of these systems employ the Advanced Encryption Standard algorithm in order to achieve a secure mode of operation. Since this algorithm is of a high computational complexity, this paper utilizes various hardware-software co-design...
This paper presents the architecture and implementation of a configurable router intended for embedded network-on-chip support within field-programmable gate arrays. The router supports five network topologies and utilizes a dual-crossbar arrangement to reduce resource utilization. The router has been implemented in an Altera Stratix chip and in a 0.18-mum standard-cell process. For the routing and...
Warp processing dynamically and transparently transforms an executing microprocessor's binary kernels into customized field-programmable gate array (FPGA) circuits, commonly resulting in 2X to 100X speedup over executing on microprocessors. A new architecture and set of dynamic CAD tools demonstrate warp processing's potential.
Early detection of system failure required continuous monitoring of electro-mechanical system which required embedded prognostics devices. Unfortunately, the current research and industrial solutions do not provide a user friendly and rapidly configurable environment to create 'adaptive microprocessor size with supercomputer performance' embedded solution in order to reduce downtime. Developing a...
Expanding the software concept, to spatial models like circuits facilitates programming next-generation embedded systems. Today, embedded-system designers frequently supplement microprocessors with custom digital circuits, often called coprocessors or accelerators, to meet performance demands. A circuit is simply a connection of components, perhaps low-level components like logic gates, or higher-level...
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