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In this paper, a new wide-band low-voltage low-power mixer is proposed. Using a modified stacked topology in conjunction with current bleeding technique, the mixer has a power consumption of 10mw while it uses a voltage supply of 1.2 V. Parallel peaking inductors are used to increase the RF frequency and broaden the bandwidth of the mixer. The 3-dB RF frequency band of the mixer is form 7GHz to 15GHz,...
This paper studies the customized differential stacked spiral inductor (DSSI) and transistor layout designs for broadband high-speed circuits. Compared with the inductor provided in foundry process design kits (PDK), the DSSI increases the inductance density by 3 times and at the same time enlarges the self-resonance frequency by 11.5%. The impact of different differential pair layout styles is compared...
We present the design and characterization of a broadband, low-noise transimpedance amplifier (TIA) with adjustable gain-peaking, implemented in 65-nm CMOS. The TIA exhibits 40-GHz bandwidth, 20-dB gain and consumes 107 mW power. An additional continuously-tunable 12-dB gain-peaking near 40 GHz is available through a simple yet effective tuning mechanism, consuming only 14% more power. The adjustable...
This paper presents low-cost small-area DC-to-8GHz packaged and ESD-protected wideband LNAs and a wideband fractional-N frequency synthesizers implemented in CMOS technologies for reconfigurable radio applications.
This work first generates ±1 V output via the self-startup pulse transformer boost converter. Another on-chip single-stage voltage tripler then generates 3 V output from the extra output power of boost converter, which is shunted otherwise. Higher voltage headroom is instrumental for sensor, analog and RF circuits. Charge pump clock frequency is adaptively tracking the input voltage, which is sensed...
A simplified output matching network for pulse width modulated Class-E Power Amplifier for efficiency enhancement at back-off power level is proposed. The shunt capacitance and the series inductance in the Class-E PA are realized through capacitor banks that are tuned according to the duty cycle to meet ZVS conditions. The differential PA design is implemented in 130 nm CMOS technology achieving maximum...
This paper presents the design and simulation of High gain Source degenerated Cascode LNA for Wi-max and W-CDMA applications at 3.5GHz. The design uses an enhanced cascade topology to attain improved forward gain and noise figure. Th is design includes lumped elements like inductor, capacitor and resistors to design input and output matching networks. The targeted narrow-band gain, impedance matching...
The design and analysis of down-conversion mixer for high-band applications between 6–15GHz is presented in this paper. The mixer proposed is based on folded double-balanced Gilbert cell topology which is good for low-voltage use and well-balanced performances. Two on-chip inductors are introduced for biasing and reducing flicker noise. By setting the bias separately, both the LO stages and trans-conductance...
Authors such as Thornton, Kuh, and Glasser have considered bounds on possible oscillator frequency and amplifier bandwidth based on regions of the Laplace-transform s-plane where a set of components cannot achieve real and reactive power balance. We define a “gain” that is analytic and less than unity in magnitude for values of s where power balance cannot be achieved. We then derive bounds on amplifier...
This paper presents a high speed and low distortion sampler with two-channel time-interleaved sampler with track-and-hold amplifier (THA). The THA is based on switched source-follower with active inductor load such that wide bandwidth in tack-mode and small signal feed-through in hold-mode can be both achieved within compact area. Furthermore, one clock-controlled auxiliary transistor is also introduced...
In this paper, a novel positive transformer feedback down-conversion mixer is proposed to boost conversion gain. An ultra-wideband RF input is achieved by feeding RF signal at the emitter of the switching pair. Switching devices are biased so as to minimize LO input power. Area is minimized by means of transformer coupling and shielded transmission line for RF routing. The proposed mixer is implemented...
To achieve a large bandwidth without inductor peaking, this work presents an inductor-less bandwidth-extension technique to establish Multi-Level Active Feedback (MLAF) structure that is used in a CMOS differential Trans-Impedance Amplifier (TIA). The proposed TIA consists of a trans-impedance stage, a low-pass filter, a gain stage, and an output buffer. The trans-impedance stage adopts the regulated...
A 0.1–1.2 GHz power amplifier using 0.18-µm CMOS technology is presented with a small chip area. With 3.3V supply, the measurement results in this band indicated that the gain is better than 20 dB, the S11 and S22 is less than − 18 dB and −10 dB, respectively. The saturated output power is 20.5 dBm and 19.5 dBm at 433 MHz and 900 MHz with the corresponding PAE of 27% and 19.5%, respectively. The chip...
A 100 Gb/s CMOS transimpedance amplifier (TIA) for high speed optical communication receivers is presented in this paper. The TIA is based on a differential architecture and composed of a regulated cascode block and a differential amplifier with active feedback. It adopts peaking inductors and a capacitive degeneration scheme to increase the bandwidth. The TIA is designed and laid out in CMOS 65 nm...
All wireless communication products must meet the reliability specifications during mass production. To prevent from electrostatic discharge (ESD) damages, the ESD protection designs must be added at all input/output pads in chip. Some ESD protection designs with low parasitic capacitance for radio-frequency (RF) applications are reviewed in this paper. Besides, a novel ESD protection design is proposed...
This paper presents a current-mode adaptively hysteretic control (CMAHC) technique to achieve the fast transient response for DC-DC buck converters. A complementary full range current sensor comprising of charging-path and discharging-path sensing transistors is proposed to track the inductor current seamlessly. With the proposed current-mode adaptively hysteretic topology, the inductor current is...
A low-power dual-band complementary metal-oxide semiconductor (CMOS) low-noise amplifier (LNA) for wireless local-area network applications is presented. The switched external capacitor is added to the gate-source node of the input transistor, which match to the input port in two frequency bands of 2.4 and 5.2 GHz. By just adding a small-size switched capacitor to the conventional source-degenerated...
This paper presents a design of an area-efficient 10-GHz PLL for source-synchronous, multi-channel applications. To be applied in the multi-channel application, the proposed PLL is implemented without use of any high-cost inductor to minimize silicon area while achieving 10-GHz operation frequency. A modified CML type ring-VCO is used to make the VCO outputs have consistent signal amplitude. The proposed...
Design information is given for developing microwave and millimeter-wave silicon based low noise broadband monolithic transimpedance amplifiers. The required layout optimizations for SiGe HBTs and CMOS devices are described and the foundry selection criteria we employed are reported. An efficient high frequency passive devices implementation and high frequency connectivity solutions with external...
A CMOS digitally programmable lossless floating inductor is proposed. The proposed inductor is based on current feedback operational amplifier and resistor array to provide digital tuning of the inductance value. The presented block realizes a programmable floating inductor tuned from 0.4167mH to 5.67 mH. As an application for the proposed circuit a resonant circuit and low pass filter have been realized...
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