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A millimeter-wave bond-wire packaging and micro-strip to waveguide transition are proposed for E-band CMOS power amplifiers. A 700μm cavity is used to shorten bond-wire length, and the bond-wire inductance is compensated by micro-strip matching network, realizing a good packaging performance with 0.3dB loss over 30GHz bandwidth. A low-cost Alumina board is used for micro-strip to waveguide transition,...
Millimeter-wave on-off keying (OOK) modulator for wireless inter-chip communications is proposed. The proposed modulator not only has a wide bandwidth which allows the high speed modulation but also operates with a low power consumption enhancing the power efficiency and assures the inter-chip communication. With wide bandwidth and the OOK modulation scheme, it can process data having 12 Gbps while...
This paper presents a 120 GHz low power, high gain, wideband active balun design in 65nm CMOS. The active balun is realized using current-reuse cascode topology and common source topology. The active balun exhibits a measured small signal where S21 and S31 are -5 ± 1.3 dB and -4.8 ± 0.5 dB, respectively, from 113GHz to 133 GHz. The measured gain imbalance and phase imbalance is kept less than 1.5...
A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBΩ transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance,...
A 5–20Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) using edge counting is fabricated in 40-nm CMOS technology. The power of this CTLE is adjusted according to the bit rates to improve the power efficiency. An edge counting technique with an asynchronous clock is presented to adaptively adjust the gain and power of this CTLE. All the measured bit error rates are less than 10...
This paper presents a 26.5 Gb/s optical receiver with an all-digital CDR (ADCDR) fabricated in a 65 nm CMOS process. The receiver consists of a transimpedance amplifier (TIA), a limiting amplifier (LA), and a half-rate ADCDR. The TIA and LA are based on an inverter-based amplifier for low power consumption. The ADCDR adopts an LC quadrature digitally controlled oscillator (LC-QDCO) for the quadrature...
A supply-current equalizer disables a Correlation Power Analysis (CPA) attack on an AES cryptographic processor. An intermittent equalizer operation only at processing rounds critical to key disclosure suppresses the equalizer power overhead significantly. For this low-power intermittent operation, a Thru operation mode is proposed with minimum hardware overhead. A level-shift comparator hides its...
This paper describes a fully integrated E-band transmitter (TX) in 40-nm CMOS. Circuit, layout and calibration techniques are presented to suppress the LO feed-through (LOFT) and I/Q imbalance over both 71–76 and 81–86 GHz bands. A systematic design methodology is proposed for the millimeter-wave poly-phase filter (PPF) to achieve lowest I/Q imbalance with minimum EM simulations. The 40-nm E-band...
Within this work the complete design and characterization of a 10bit Analog to Digital Converter (ADC) for a sample rate up to 100MSps is presented. Therefore pipeline architecture with a series of 1.5bit stages has been realized. Each stage contains a sub-ADC (two high speed comparators and a latch) and a multiplying DAC (switched capacitor feedback circuit with a high gain folded cascode operational...
This paper presents optimization process, simulations and measurement results of a fully differential 60 GHz active down converter with resonating current bleeding in a 90 nm CMOS process. The circuit is thought to be used within a superheterodyne receiver with intermediate frequency at around 20 GHz, covering the four channels of the IEEE802.15.3c standard. Thanks to the careful optimization of the...
This paper presents a small size 60 GHz Antenna-on-Chip (AoC) designed and fabricated using 0.18 um TSMC Complementary Metal Oxide Semiconductor (CMOS) process. AoC performance is enhanced using asymmetric Artificial Magnetic Conductor (AMC). The AoC area including the AMC is 1715 um by 710 um. As AMC shields AoC from the lossy CMOS substrate, simulated gain of −0.25 dBi is achieved at 60 GHz for...
A CMOS-based microelectrode array (MEA) with 4225 recording sites and 1024 stimulation sites and a related data acquisition system are presented. The chip provides high spatiotemporal resolution on an active area of 1 mm × 1 mm or 2 mm × 2 mm, respectively, and allows in-vitro neural tissue interfacing experiments with full imaging capability. The entire chip surface is covered by a thin high-k dielectric...
High-sensitivity rapid direct bacteria counting is an essential key method for point-of-care testing. Counting pathogens (cells, viruses, and bacteria) directly in real time with high sensitivity is useful in maintaining human health and preventing pandemics or bioterrorism. However, conventional counting methods with high sensitivity such as the polymerase chain reaction and cultivation-based biochemical...
An extended-gate CMOS sensor array with enzyme-immobilized microbeads for redox-potential glucose detection is demonstrated for the first time. Redox-potential detection has the possibility to achieve high accuracy because it is not affected by the buffer conditions. Despite this high-accuracy property, redox-potential detection requires a sufficient amount of enzyme, which leads to increased cost...
A CMOS sensor platform with a bacteria-sized (1.2 µm × 2.05 µm) Au electroless-plated 1024 × 1024 microelectrode array for high-sensitivity rapid direct bacteria counting is demonstrated. For high-sensitivity direct pathogen counting, Au microelectrodes are required to be as small as the target cell. In this work, by improving a self-aligned electroless plating technique, the size of microelectrodes...
A low-power, 160 MS/s, single-channel pipelined SAR ADC is presented. The ADC frontend employs two capacitive DACs that decouple the high-speed SAR operation from the low-noise residue generation, thereby improving both speed and power dissipation. Measured results show an SNDR of 68.3/66 dB at low frequency/Nyquist inputs, respectively, which corresponds to a FOMS of 167/164.7 dB. The converter core...
A 18 to 24-GHz broadband power amplifier (PA) by 0.18 um CMOS technology is presented in this paper. The low loss microstrip line matching technique is used to reduce transmission losses and achieve higher gain, PAE and enough output power. An improved Gain-boosting technique is also included in the PA architecture to improve high frequency gain and gain flatness. The measurement results show that...
A 10-Gb/s 6-Vpp differential Mach-Zehnder modulator driver is implemented in 65-nm CMOS technology. The proposed modulator driver adopts a triple-stacking topology with a dynamic biasing to generate the differential voltage swing of six times as much as the nominal supply. The modulator driver occupies only 0.04 mm2 without using inductors for area efficiency. The measurement results show an operating...
This paper describes a CMOS interface circuit for silicon photonics. 20-Gb/s operation of an optical receiver front-end circuit is demonstrated using an optical signal applied to the optical front-end. The transimpedance amplifier (TIA) is based on an inverter with resistive and inductive feedback for low power consumption and frequency compensation. A negative capacitance generation is employed in...
We present a 1-GΩ CMOS transimpedance amplifier (TIA) suitable for processing sub-nA-level currents in electrochemical biosensor signal-acquisition circuits. Use of a two-stage active transconductor provides resistive feedback in place of a single large-area linear resistor. We engineer the TIA feedback loop to suppress output offset caused by dc input leakage currents of ±0.9 nA. We also implement...
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