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This paper proposes a new flash time-to-digital converter (TDC) design, which incorporates deterministic, variable delay into the decision elements. These are implemented with cross-coupled NAND standard cells of variable transistor widths. Both experiment and simulation are used to validate this new design, which provides variable time-difference ranges by controlling the input slew rate. It is also...
A new camera technology for high-speed color scanning is presented that is based on a novel multi-line CMOS color image sensor. A pixel matrix consisting of multiple red-, green-, and blue-sensitive lines allows acquisition of dense RGB color information at every pixel location including the possibility of improving the signal to noise ratio by summing up multiple exposures in the analog domain of...
A 5bit 1GS/s 0.05mm2 4× time-interleaved asynchronous digital slope ADC in 90nm CMOS for IR UWB radio is presented. New delay cells are introduced to double the speed over prior art, yielding the 250MS/s single-channel slope converter. A self-disabled comparator eliminates static leakage and consumes only 0.25pJ/conversion. A single calibration circuit corrects both offset errors and mismatches in...
This paper presents an 18-to-32-GHz ultra wideband (UWB) low-noise amplifier (LNA) in a bulk 0.13-µm CMOS technology. The LNA consisting of four stages exhibits a flat gain of 14.5 ± 1.5 dB over the entire 18-to-32 GHz and a noise figure of 5.5 ± 0.4 dB at K-band (18 to 26.5 GHz). Moreover, the group delay variation is suppressed as low as 63.5 ± 6.5 ps over 21–26 GHz. The wideband characteristics...
In this work, we demonstrate the use of a non-traditional logic for the implementation of a dual-modulus prescaler. The proposed prescaler consumes less power than TSPC designs and is faster than ETSPC designs. The maximum speed reaches up to 96% of that of a single divide-by-2 D-flip-flop, the theoretical limit. Implemented in 130-nm CMOS technology, the maximum input frequency reaches 14.1GHz with...
Data stability is a primary concern in today's high performance memory circuits with deeply scaled transistors and power supply voltages. Recently proposed eight-transistor (8T) Static Random Access Memory (SRAM) cells offer enhanced data stability as compared to the conventional six-transistor (6T) SRAM cells by isolating the bitlines from data storage nodes during a read operation. Novel multi-threshold-voltage...
In this paper, we report the design of an amplifier with a flat group delay and gain for use in a high-speed D-band wireless transceiver without a group delay equalizer. Compared with a conventional amplifier with a group delay equalizer, the amplifier have achieved a decrease in the power consumption and an increase in the communication speed. The peak gain is 8.1dB at 118.6GHz with a power consumption...
Bias Temperature Instability (BTI) becomes one of the most important reliability issues for nanometer process devices. We focus on aging degradation by BTI because it is known as one of the dominant factor that determines life time of circuits. In this paper, we show circuit delay degradation characteristic of BTI using the circuit simulation. The delay increase 15% after 10 years stress.
This paper presents the first system-level study on the impact of carbon nanotube field-effect transistors (CNFETs) on multilevel interconnect networks. In this paper, for the first time, the gains in speed and energy-delay product (EDP) offered by CNFETs over CMOS are presented as a function of interconnect length. It is demonstrated that the respective 4.3× and 8× improvements in intrinsic delay...
This paper presents a dynamic latched comparator suitable for applications with very low supply voltage. It adopts a circuit topology with a separated input stage and two cross-coupled pairs (nMOS and pMOS) stages in parallel instead of stacking them on top of each other as previous works. This circuit topology enables fast operation over a wide input common-mode voltage and supply voltage range....
In this research we present a new programmable pulse pre-shaper to efficiently reduce the overshoot of second order electric and electronic systems. In the proposed design, the input step pulse is passed from the delayed unit. The delay unit changes the arrival time of input pulse with different controlled digital input lines values for rising and falling edges. Then the resulted delayed pulse is...
The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality on a chip. Scaling helps to increase speed and frequency of operation and hence higher performance...
In this communication, an ultra-compact I–V nanometer MOS model is used to predict the dynamic characteristics (propagation delay and rise/fall times) of CMOS inverter and more complex stacked-transistor gates. Simulations reveal typical errors within 1–3% (always less than 6%) for the simple inverter case and within 4–8% (always less than 11%) in the case of stacked-transistor gates.
In this paper, a new overshoot cancellation method is presented for comparator-based pipelined ADCs. By introducing charging and discharging operations in two adjacent stages, the large overshoot in each stage can be either tolerated as sub-ADC error or cancelled out with each other. Applying this concept, a 10-bit pipelined ADC has been designed and simulated in a 0.18-µm CMOS process. It achieves...
Subthreshold voltage operation enables digital systems to operate at ultra-low energy levels. However, as the voltage is reduced into subthreshold, the required safety margins become unrealistically large due to exponential dependencies. These margins can be addressed in a system by sensors, replica-path circuits, or timing error detection (TED). Each of these methods require additional energy overhead...
This study presents a 6-Gb/s clock and data recovery (CDR) for the high-speed data transmission systems. Similar to the concept of the oversampling CDR, the proposed CDR presents an alternative scheme, which uses the data delay window (DDW) and a sensing-amplified phase detector (SAPD) to substitute the conventional DFF-based PD. It shows that the NRZ data could be aligned and recovered by the only...
We present a digital phase interpolator (PI) design for 65nm CMOS that avoids conventional analog structures, accurately achieves 2-bits phase resolution across a range of rise time and input delays from trise: 48ps → 200ps using a ratio trise/tdelay of at least 1 or greater. Increased accuracy is available for certain rise times using ratios increasing between 1 and 10 as verified by simulations...
A clock-deskewing circuit (CDC) using a dual delay-locked-loop technique is presented. The CDC can synchronize the clocks for a chip-to-chip system without delay measurements and dummy delay elements. Simulated in a 0.18µm CMOS technology, the maximum operating frequency is 1.5 GHz and the cycle-to-cycle clock jitter is 7.74 ps. Total power dissipation of the CDC is 56mW under a 1.8-V supply.
This paper discusses about the design of a novel and fast 4-2 compressor. To enhance the speed performance, some changes are performed in the truth table of conventional 4-2 compressor which leaded to reduction of gate level delay to 2 XOR logic gates plus 1 transistor for all parameters. Because of similar paths, there will be no need for extra buffers in low latency paths to equalize the delays...
A novel high speed Carry Look Ahead Adder (CLA) is presented. The proposed CLA is implemented using Dual Mode Logic (DML) methodology, as recently introduced by our group. DML allows dynamic switching between static and dynamic modes of operation. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit...
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