The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Fast design space exploration of complex nano-CMOS mixed-signal circuits is an important problem. In this paper, a design process flow that uses metamodels is introduced. In this flow the most important task is the sampling of the design space. In this paper, different sampling techniques for producing an accurate metamodel are investigated to minimize the number of samples required by using a nano-CMOS...
In this paper, Amplitude Shift Keying (ASK) demodulator of Radio Frequency Identification (RFID) tag module is designed as low power. RFID tag is pursued the least area, low price and low power. And the proposed ASK demodulator is designed without resistors and capacitors, differing from the existing ASK demodulator. Also, the proposed ASK demodulator is designed without envelope detector and Schmitt-trigger...
In this paper a UWB pulse generator for wireless inter and intrachip communication is introduced. The transmitter produces BPSK-modulated ultra-short Gaussian monocycle pulses of average duration 74ps. The circuit was implemented and simulated in HSPICE using IBM 90nm CMOS technology with a supply voltage of 1.2V. The transmitter performs at an input bit-rate of 10Gbps. The circuit has a low average...
This paper proposes a new theory of adder and its basic structure. The new adder is an asynchronous adder whose basic unit is half adder, called Parallel Feedback Carry Adder (PFCA) as its carry mode is parallel feedback. In theory, compared to the adders (e.g. RCA, CLA, CSeA) based on full adder, PFCA is faster in speed and smaller in area. A CMOS gate implementation is proposed to verify the new...
FinFET device, the promise one of all candidates which may extend CMOS scaling to 10nm and beyond, has attracted intensive research interest in recent years. In paralleling the process technology and circuit design methodology, a compact model which serves as a link between the process technology and circuit design is strongly demanded. In this paper, we first review the FinFET process technology...
In this paper, we study the effect of the variation of process parameters on the performance of a voltage controlled oscillator (VCO) and an inverter with technology scaling. The spread in performances is shown to be Gaussian in nature, considering the fact that the distributions of process parameters are also Gaussian in nature. The spreads in performances increase with technology scaling. These...
Content Addressable Memory (CAM) is a data storage device, utilizing the Static Random Access Memory (SRAM) cell. CAMs are very popular especially implemented in network routers for IP address lookup, packet forwarding and packet classifications. Up to now, there are many types of CAM to conform to these different implementations. For the purpose to estimate the efficiency and power distribution of...
This paper proposes a fast, precise transient response and frequency characteristics simulation method for switching converters. This method uses a behavioral simulation tool (MATLAB/Simulink) without using a SPICE-like analog simulator. The nonlinear operation of the circuit is considered, and the nonlinear function is realized by defining the formula based on the circuit operation and by applying...
This paper introduces Spicedim, a graphical programming interface for integrated CMOS circuit design. It connects the SPICE netlist level to an easy to use programming language, both combined in a graphical development environment. After classifying the context of this tool the fundamental application for parametric circuit simulation and signal processing is shown. This is done at the example of...
Most neural networks have a basic competitive learning rule on top of a more involved processing algorithm. This work highlights three basic learning rules - winner-take-all (WTA), spike timing dependent plasticity (STDP), and inhibition of return (IOR). It also gives a design example implementing WTA combined with STDP in a position detector. A CMOS and an MMOST (Memristor-MOS Technology) design...
In this paper a new low voltage low power class AB CMOS second generation current conveyor (CCII) based on Rail-to-Rail folded cascode Op-Amp is presented, with a great performance. The proposed CCII provides very low input impedance at X-port, very high input impedance at Y-port, accurate voltage and current tracking with low offset, and wide bandwidth. As an application, a four quadrant analog multiplier...
This paper presents a new method to recover energy in an Analog-to-Digital Converter (ADC) based on the principle of adiabatic charging. The ADC comprises an Adiabatic Charging Charge Redistribution (ACCR) DAC, a dynamic comparator, and a Successive-Approximation-Register (SAR) counter. Charges in the ACCR DAC can be recovered through a resonant power supply and adiabatic switch. These charges can...
The operational amplifiers (Op-Amps) are the essential building blocks of many electronic circuits with wide applications. However, the operational amplifiers suffer from oscillation on their output (especially when are used in feedback loops) which leads to instability. This problem could be seen in step response of operational amplifiers as percent overshoot (P.O.). In this paper, a novel Posicast-based...
As CMOS technology is scaled down, the supply voltage and gate capacitance are reduced, which results in the reduction of charge storing capacity at each node and increase of the susceptibility to external noise in radiation environments. In this paper, a novel hardened latch design is proposed and compared with the previous hardened latch designs using 32nm technology node. Extensive simulation results...
A systematic methodology for opamp synthesis is presented. Based on this methodology, an automatic computer-aided design (CAD) tool called OTACAD is developed. OTACAD directly uses HSPICE as the simulator and a lookup table to model MOSFET in saturation region without complex equations. So it can design opamps in deep-sub-micron technologies and is suitable for various CMOS processes. Then, A sample...
This paper presents a design of a high-performance sample-and-hold (S/H) circuit. Switches' constraints on signal settling in charge-transferring S/H circuit are discussed. Then the optimum combination of switches for this S/H circuit is proposed. Hspice simulated results based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows a 103dB SFDR, 86dB SNDR at Nyquist input @ Fs=125MS/s...
A design of a 3.5 + 1-bit multiplying digital-to-analog converter (MDAC) which can be used in the first stage of a 14-bit 100MS/s pipelined analog-to-digital converter (ADC) is presented in this paper. Two decision levels are added in the MDAC so that bi-directional overflow of the input signal can be detected. Bootstrap structure with a buffer is proposed to prevent the large bootstrap capacitance...
For applications requiring low-power low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed. Marr mother wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method, the optimum parameters of this function are obtained.The circuits of implementating...
Innovation of ISFET with electrochemical and silicon technology has the advantage of ease of integration with associated signal processing, simplicity, portability and potential on-site screening. ISFET sensor plays a critical role in biomedical instrumentation system. It serves at the front end of instruments in signal acquisition and conditioning circuit, interfacing between the electronic signals...
Equation-based optimization using geometric programming (GP) for automated synthesis of analog circuits has recently gained broader adoption. A major outstanding challenge is the inaccuracy resulting from fitting the complex behavior of scaled transistors to posynomial functions. Fitting over a large region can be grossly inaccurate, and in fact, poor posynomial fit can lead to failure to find a true...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.