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The reduction in the transistor and interconnect dimensions have a severe impact on the reliable performance of the Field Programmable Gate Array (FPGA) circuits. The process variation effects in nanometer scale technologies result in transient errors or permanent failures that cause undesired behavior of the circuit. In this work, we analyze a method for fault identification to mitigate the impact...
This paper presents an evolutionary fault recovery scheme using Evolvable Hardware (EHW) to have reliable computations. The scheme is based on Genetic Algorithm as Evolutionary Algorithm used in EHW and uses Look Up Tables (LUTs) as basic reconfigurable elements. The scheme can recover a component with more than one fault and uses limited spare cells. The recovered hardware shows reasonable functionality...
As technology feature sizes shrink, aggressive voltage scaling is required to contain power density. However, this also increases the rate of transient upsets -- potentially preventing us from scaling down voltage and possibly even requiring voltage increases to maintain reliability. Duplication with checking and triple-modular redundancy are traditional approaches to combat transient errors, but...
As process scaling and transistor count inflation continue, silicon chips are becoming increasingly susceptible to faults. Although FPGAs are particularly vulnerable to these effects, their runtime reconfigurability offers unique opportunities for fault tolerance. This work presents an application combining algorithmic-level error detection with dynamic partial reconfiguration (DPR) to allow faults...
In last decades many techniques for fault tolerant system design in the field of reconfigurable hardware were presented. Some of them use the partial reconfiguration for the repair of component affected by the fault to extend the operational time of the system. The majority of these techniques is focused on transient fault mitigation which are more frequent. But the partial reconfiguration can be...
This paper describes research efforts to mitigate weaknesses in a TMR+spares radiation tolerant SRAM-based FPGA computer system. An existing 9-tile Microblaze architecture is reviewed and the desired improvements of fault-mitigated routing, fault location determination and performance enhancement via runtime-configurable hardware accelerators are discussed. Hamming encoding is proposed as a method...
Digital electronic systems in automotive applications are in charge of different tasks, ranging from very critical control functions (e.g., airbag, ABS, ESP) to comfort services (e.g., handling of mirrors, seats, windows, wipers). Hardening these systems involves suitably trading off cost and reliability. Due to standards and regulations in the area, the reliability of subsystems involved even in...
As CMOS feature sizes are shrinking, manufacturing defects are becoming a growing concern in micro and nanoelectronics. This work deals with defect tolerance in FPGAs that are surely affected by technology downscaling. In this paper, we are interested in enhancing the defect tolerance of a switch box in a mesh of clusters FPGA, while trying to reduce the hardening cost. First, we had to spot, among...
Field Programmable Gate Arrays (FPGAs), as any other electronic devices, are designed according to some life expectancy figures. For this reason, its lifetime is finite given due to appearance of faults caused by the natural physical degradation. In this paper, we present a low cost solution for autonomous detection of faults at the end of FPGAs life cycle. Our proposed methodology starts from a pre-analysis...
This paper introduces a novel end-to-end platform called PERSim that allows FPGA accelerated full-system simulation of complete programs on prototype hardware with detailed fault injection that can capture gate delays and digital logic behavior of arbitrary circuits and provides full coverage. We use PERSim and report on five case studies spanning a diverse spectrum of reliability techniques including...
Fault handling is an important metric for many operating environments. The traditional technique for improving reliability of system is by replicating the system component. This paper explains about the Adaptive group testing technique for isolating the faults which is present in the memory of the system. The memory element contains many cell and these cells are grouped into number of blocks. These...
The very high levels of integration and submicron device sizes used in emerging VLSI systems and FPGAs lead to frequent occurrences of defects and operational faults. Thus, the need for fault tolerance and reliability of deployed systems becomes increasingly prominent. This paper discusses fault tolerance and reliability observed in the design of a parallel self-healing VLSI system, based on partial...
This paper presents the non-intrusive built-in self-test system (BIST) for the test pattern generator (TPG) and output response analyzer (ORA) for testing of the field programmable gate array (FPGA). It consists of software and hardware parts with channels in between them to establish communication. The test generation and the response analysis are done in the software part whereas the hardware part...
To protect the Intellectual Property of Integrated Circuit, We present a novel architecture which exploits and analyze error information produced by an embedded timing-fault execution unit in the data path of a microprocessor. As the timing of the fault execution circuit doesn't meet microprocessor global timing requirement intentionally, the computation result appears randomly error and will depend...
As bank IC cards with chips are widely used nowadays, the security of them becomes increasingly important. Fault attack, which aims to inject fault into the chip during the calculation, is a serious threat to the information security of the chip. Thus considerable countermeasures are involved to meet the overall requirements and facilitate the intended application for bank IC cards. In this paper,...
While we reap the benefits of process scaling in terms of transistor density and switching speed, consideration must be given to the negative effects it causes: increased variation, degradation and fault susceptibility. Above device level, such phenomena and the faults they induce can lead to reduced yield, decreased system reliability and, in extreme cases, total failure after a period of successful...
In this work, we intend to demonstrate a number of reliability techniques developed for Coarse Grained Reconfigurable Architectures (CGRA). The techniques to be demonstrated target different portions of a System on Chip (SoC) Design consisting of a general purpose CPU, various accelerators and a CGRA which may be used for application acceleration as well. On the CGRA we will demonstrate a light-weight...
This paper proposes a full-featured fault injection framework to assess reliability of FPGA-based designs. The framework provides non-intrusiveness, portability, flexibility and performance in reliability evaluation of FPGA-based designs against adverse effects of SEUs. It works in a non-intrusive manner, allowing the reliability of ready-to-be-released designs to be assessed independently, without...
In this paper, we propose the implementation of multiple defect-tolerant techniques on an SRAM-based FPGA. These techniques include redundancy at both the logic block and intra-cluster interconnect. In the logic block, redundancy is implemented at the multiplexer level. Its efficiency is analyzed by injecting a single defect at the output of a multiplexer, considering all possible locations and input...
This paper presents an analytical method of shared spare redundancy in fine granularity for reconfiguration system. The particularity of spare redundancy lies that the spare unit for replacement is available for more than one functional unit. To analyze the reliability of this special redundancy system, the structure function is re-defined and the replacement matrix is proposed to represent the system...
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