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This paper describes the design and testing of a radiation tolerant, low-cost computer system for use in small satellites. The computer is implemented on a modern Field Programmable Gate Array, which enables the novel fault mitigation strategy to be deployed on a commercial part, thus reducing the cost of the system. Using a modern processing node also provides increased computational performance...
Complementary metal-oxide-semiconductor (CMOS) on Silicon is the most commonly used process for digital circuit design. Other processes include Silicon bipolar, GaAs, SiGe, Bi-CMOS or Silicon on insulator (SoI). The models built in this work is based on CMOS process. However, all techniques discussed in this thesis are technology independent, with minor differences arising from circuit implementations.
On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of...
A prototype system has demonstrated the capability to use a custom-designed multi-channel sensor to monitor high energy radiation strikes by coupling the silicon sensing elements with a radiation tolerant computer system. The computer system uses triple modular redundant soft processors and custom signal conditioning circuitry to monitor single event effects caused by high energy particles passing...
Memoryless codes are a class of CACs in which data words and codewords have a 1-to-1 mapping. The encoder uses a fixed codebook and it output is independent of the previous transmitted codewords, hence memoryless.
Codewords generated inmemory-based crosstalk avoidance encoding satisfy a specified crosstalk upper-bound requirement with respect to the previous codeword on the bus. The codeword is generated based not only on the current data word, but also on the previously transmitted codeword. Such a code is therefore called „memorybased code“. The decoder also uses the current received codeword and either the...
The use of advanced packaging will reduce the electrical parasitics due to the package. This reduces the package noise in the system which leads to increased performance; however, moving toward advanced packaging is often more expensive and can result in a cost prohibitive increase in the majority of modern VLSI designs.
The performance of an off-chip bus depends on how fast the digital output drivers can switch the output voltage levels. This relates to how much data that one pin of the bus can transmit per second. The term Unit Interval (UI) represents the shortest amount of time that data can be present on an individual pin and still accurately transmit the logic value from the Transmitter (Tx) to the Receiver...
The construction of an IC must accomplish many tasks. The first is to electrically connect the signals on the IC to the signal paths on the system PCB. The second is to electrically conduct power from the system PCB to the devices on the IC. In addition, the package must provide mechanical protection for the IC as well as thermal dissipation. The typically consists of two levels of interconnect. The...
Impedance mismatches between the IC package and the system PCB cause reflections that lead to unwanted noise in the system. This noise limits the maximum datarate that a package can achieve (Equation 11.26). As described in Section 8.2, the impedance of the package interconnect is dictated by the self-inductance and self-capacitance of the physical structure in addition to its mutual inductance and...
When determining the performance of an off-chip bus, the worst-case noise magnitude must be considered in order to ensure a robust digital system. Chapter 11 presented an analytical model to predict the performance of an off-chip bus using the assumption that each of the noise sources within the package contributes its worstcase noise. Each source of noise within the package (Section 8.2) had a particular...
Integrated circuit (IC) performance has increased at an exponential rate since the first patent was issued to Robert Noyce of Fairchild Semiconductor in 1961 [10]. Since the advent of the IC, the number of transistors on an integrated circuit has roughly doubled every 18 months. This trend, also known as Moores Law [96], has been consistently met over the past 45 years. This increase in system performance...
So far, the discussions on on-chip crosstalk avoidance have been limited to binary valued busses. This can be attributed to the fact that binary-valued busses are almost exclusively used for on-chip interconnects in todays digital circuits thanks to their seamless ability to interface with to the logic circuit. Further, binary-valued busses result in simple driver and receiver designs, with low power...
Application specific integrated circuits (ASICs) have enabled the dramatic increase in computational power that digital systems have enjoyed over the past 20 years; however, within the past 5 years, the cost associated with designing and fabricating an ASIC has increased considerably [40]. This cost stems from the increased complexity of the design process, along with the high cost of manufacturing...
Conventional wisdom doubts that bus encoding would ever become a viable solution to the problem of inter-wire capacitive crosstalk due to its area overhead and CODEC complexity associated with such techniques.
This monograph has presented a comprehensive look at the noise problems within IC packaging. Todays integrated circuits are experiencing a dramatic increase in performance due to significant advances in the IC design and fabrication processes. IC technology has followed Moores Laws for the past 30 years and is expected to continue at this rate sometime into the next decade. At the same time, IC packaging...
It was shown in Chapter 13 that the performance of an off-chip bus could be increased by avoiding a subset of patterns which resulted in noise greater than a specified limit. By eliminating the patterns that create the greatest amount of noise, the remaining patterns can be transmitted at a faster per-pin datarate without exceeding the user-defined noise limits of the system. The bus expansion encoding...
A bus is defined as a group of signals that transmits data from one circuit to another. When designing a bus that traverses a package, the number of physical interconnect paths must be accounted for. This means that in addition to the total number of signal pins that are needed, the number of power and ground pins associated with the bus must also be considered. In VLSI design there are typically...
The 1C-free bus described in Section 3.3 does not require CODECs, or we can say that these CODEC designs are trivial (repeating the input bit by N times). On the other hand, 3C-free (Section 3.1) and 2C-free (Section 3.2) codes need CODECs. For these codes to be used in practice, efficient CODEC designs are necessary. In the case of crosstalk avoidance codes, the complexity and speed of the CODEC...
The advancement of very large scale integration (VLSI) technologies has been following Moore’s law for the past several decades: the number of transistors on an integrated circuit is doubling every two years [4] and the channel length is scaling at the rate of 0.7/3years [68, 41]. It was not long ago when VLSI design marched into the realm of Deep Submicron (DSM) processes, where the minimum feature...
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