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A new readout integrated circuit (ROIC) for multispectral classification is presented. The ROIC is designed to utilize the spectral response tunability of dot-in-a-well (DWELL) infrared photodetector to exploit the possibility of real-time on-chip multispectral imaging for classification in analog domain. The unit cells are designed to include all necessary elements needed for spectral classification,...
This paper presents an energy efficient high speed DAC structure that is implemented in a 10-bit 150MSample/s successive approximation register (SAR) ADC. To reduce energy consumption and improve ADC linearity, a segmented pre-quantize and bypass architecture is proposed to avoid unnecessary switching of high-weight capacitors based on the results of pre-quantization. Time required for one bit cycling...
This paper demonstrates possible design approaches for the virtual ground fence, a novel design concept for shielding power plane noise. The basic idea of a virtual ground fence is replacing discrete capacitors with quarter-wave stubs. This allows decoupling of power plane noise in the GHz spectrum. Such noise filtering is critical in a mixed-signal system, where there is switching noise generated...
Optical encoders are sensors used to measure linear or rotational displacements in industrial and scientific equipment, such as radars, plotters, microscopes, etc. In previous papers our group presented the design of a customized photodetector array for a non-diffractive beam (NDB) optical encoder and the associated electronics. In those works the displacement was sensed by means of a generated photocurrent...
As the power demand and power failure increases, non-conventional energy sources are used to provide constant load. In this paper a new system comprising of single ended primary inductor converter (SEPIC) integrated with PV array is proposed. In the present work a model of PV array is developed and is employed as input to the SEPIC. The modeling of the SEPIC converter is developed and the operating...
Considering the space Power Conditioning Unit (PCU) needs high reliable design, especially for it works in harsh environment, a robust design and optimal method is proposed. Firstly, the mathematical model of sequential switching shunt regulator (S3R) is shown to be suitable for regulated bus power systems. Secondly, optimize the bus capacitor parameter by the parameter sweep analysis. Thirdly, when...
In this paper, a statistic based time skew calibration method for time-interleaved ADCs is presented. By comparing the mean value of the multiplication of signals in two adjacent channels, the time skew can be estimated. Subsequently, a capacitor array based digitally controlled delay block placed in sampling clock path is adopted to compensate the time skew. In addition, the precision of calibration...
In this work, the utilization of a Photovoltaic (PV) array and a battery pack in parallel via a double input DC/DC converter including a coupled inductor is reported. The dynamic performance of this proposed hybrid energy system is analyzed in detail through the switching model created in MATLAB® Simulink® environment by using PLECS® power components under different solar irradiance and demanded load...
This paper presents a novel design of a 12-bit 1MS/s SAR (Successive Approximation Register) ADC for CdZnTe (CZT) detectors application. For this SAR ADC, the main-DAC is with charge redistribution architecture to meet with low power dissipation and high speed, and the sub-DAC is a resistive divider to guarantee the linearity. To reduce the mismatches of the capacitances in the charge redistribution,...
This paper proposes a new programmable delay cell (PDC) controlled by a 4-bit binary coding inverter array and a 4-bit binary coding capacitor array for the digital impulse radio (IR) ultra wide band (UWB) pulse generator. This proposed PDC can realize an extended tuning range of pulse width with an adjustable step and reduce the cost of chip area. Simulation results show that, when implemented in...
This paper presents the concept of and an implementation technique for match enhancement in SAR ADCs. Conventionally the binary weighted capacitors in a SAR ADC are realized by combining unit capacitors and those unit capacitors are assigned to elements of the binary weighted array during layout. Note that an n-bit CR-SAR ADC has 2n unit capacitors whose capacitance values will follow a Gaussian distribution...
This paper presents the design and implementation of an 11-bit 50-MS/s split successive approximation register (SAR) analog-to-digital converter (ADC) that features a comparator with input-referred offset cancellation, an improved split capacitor digital-to-analog converter (CDAC), and a CDAC mismatch calibrator. In order to reduce the input loading capacitance of the split CDAC, an extra unit capacitor...
This paper presents a linear constant current LED driver with no off-chip inductor or capacitor. The proposed circuit consists of a main controller and constant current sources to drive the LED array. An improved control method is used for lighting the LED array step by step, shaping the output current in proportion to the input voltage. Each constant current source has functions of temperature compensation...
This paper presents a high speed parallel segmented capacitive DAC that is implemented in a 10-bit 150MSample/s successive approximation register (SAR) ADC. Compared to converters that use the conventional structure, the speed of converting one bit digital code can be 4 times faster while the power remains relatively low. In the switching procedure, a small capacitor array is used to determine the...
A 210 MS/s dual-channel 12-bit analog-to-digital converter (ADC) employing a pipelined successive approximation (SAR) architecture is presented. The ADC is partitioned into 3 stages with passive residue transferring between the 1st and the 2nd stages and active residue amplification between the 2nd and the 3rd stages. The ADC consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.48 dB at a...
Recent publications have demonstrated ADCs with ENOB > 11, sampling frequencies > 50MHz, with power < 50mW, making the SAR ADC architecture an attractive alternative to the traditional pipeline. This paper presents a production quality 11.5 ENOB, 89dB SFDR, 100MS/s SAR ADC that, including the voltage reference and digital calibration circuitry, consumes 8mW and uses 0.1mm2 in 28nm CMOS. It...
This paper proposes a novel, octagonal shaped CMOS image sensor (CIS) array for use in tandem with colored LED illumination and a corresponding, innovative pixel scanning method. The octagonal shape of the pixel array allows the CIS to make near-optimal use of silicon real estate by matching the perimeter of the pixel array to the focal plane area of lenses used in Wireless Capsule Endoscopies (WCE)...
A new highly energy-efficient SAR ADC with capacitor constructed bypass-window structure is proposed for low-power biomedical applications. The proposed structure is able to bypass the first few conversion phases when the input signal is within a pre-defined window, resulting in an overall power reduction of 59% when the input signal has a possibility of 80% to activate the bypass-window function...
A third generation of CMOS Active Pixel Sensor (APS) for high and low light imaging (HaLLI) applications is presented. The sensor pixel 128 × 128 array features more feasible and robust circuit design than its predecessors, which allows for remarkable thermal (KTC) noise suppression, bringing the anticipated noise floor below 1e- rms. A new on-focal, column parallel, two phase, Single Slope (SS) 10...
This paper presents a novel inverter topology that is applied to single-phase grid-connected photovoltaic systems. The proposed topology has an active decoupling function, which not only eliminates the double line frequency ripple power in the dc-link but also accepts large voltage ripple across the decoupling capacitor in order to reduce the requirement of the decoupling capacitance. Traditionally,...
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