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NaNet is a modular design of a family of FPGA-based PCIe Network Interface Cards specialized for low-latency real-time operations. NaNet features a Network Interface module that implements RDMA-style communications both with the host (CPU) and the GPU accelerators memories (GPUDirect P2P/RDMA) relying on the services of a high performance PCIe Gen3 x8 core. NaNet I/O Interface is highly flexible and...
We propose a design to aid experimentation with SDN architectures using legacy network equipment. We implement a portion of the design on an FPGA and evaluate throughput and latency. Results indicate viability for testbed and research environments, especially with proposed additions to further reduce latency in broadcast- and multicast-heavy traffic.
Today's applications and services become more dependent on fast wireless communication, for the upcoming years data-rate demands of 100Gbit/s can be easily expected. However, fulfilling that demand is a task which cannot simply be solved by upscaling existing technologies. While most of the research tackles the challenges regarding the transmission technology from the physical layer up to base-band...
In this paper, a real-time control network based on Ethernet and FireWire is presented, where Ethernet provides a convenient, cross-platform interface between a central control PC and a FireWire subnetwork that contains multiple distributed nodes (I/O boards). Real-time performance is achieved because this architecture limits the number of Ethernet transactions on the host PC, benefits from the availability...
With the growing ubiquity of Internet of Things (IoT), myriads of smart devices connect and share important information over the internet. In order to provide connectivity and interoperability of all the existing heterogeneous wireless devices, a full communication stack is proposed by the IoT Architecture Reference Model (IoT-ARM). From the sensor to the cloud, the proposed stack can be implemented...
This paper is presenting a field bus protocol for modular converter systems. It is optimized for minimal cycle times and synchronisation of the converter modules to ±5ns. The principle of operation is shown in detail, implemented on an FPGA based prototype system and validated by multiple measurements.
Due to the heterogeneity and complexity of systems-of-systems (SoS), their simulation is becoming very time consuming, expensive and hence impractical. As a result, design simulation is increasingly being complemented with more efficient design emulation. Runtime monitoring of emulated designs would provide a precious support in the verification activities of such complex systems. We propose novel...
This paper describes an universal interface design that allows to connect data acquisition application (DAQ) to USB bus using FPGA as a controller and USB FIFO integrated circuit as an USB protocol implementation. The designed USB FIFO to DAQ IP-core can connect a digital part of DAQ application to USB through simple I/O and streaming interfaces. The core can be used with FTDI USB FIFO ICs and Cypress...
The millimeter wave real-time imaging radar has the capabilities of high range resolution and Doppler resolution, which puts forward a new challenge for digital signal processor. Based on the analysis of technical characteristic of real-time imaging radar, a new kind of digital signal processor structure is presented. The processor adopts multi DSPs and multi FPGAs structure. And the design methods...
The paper presents a Supervisory Control and Data Acquisition System (SCADA) based on wireless communication mechanism combined with General Packet Radio System (GPRS) platform and wireless sensor networks (WSN). In order to access the services rendered by the WSNs and to extend its communication capabilities, a WSN controller was implemented with Xilinx spartan-3E, XC3S250E-4FT256C for the demand...
With the number of cores increase in systems-on-chip (SoC), bus-based approach began facing challenges to support internal communication. An alternative that has been explored is the network-on-chip (NoC), an approach that proposes to use common network knowledge on SoC projects internal communication. The standards non-adoption in the NoC components development however has delayed its wide diffusion...
Based on the technology of system on a programmable chip (SOPC), an Ethernet to fiber bridge IP core is developed and implemented in Xilinx FPGAs. The IP core provides a way to interconnect between Ethernet port and optical port, which can be used to address the needs of remote connection and break the transmission distance restriction of cable. The logic design of IP core is done in Xilinx development...
Rapid satellite deployment is the primary goal of Space Plug-and-Play Architecture (SPA), the Appliqué Sensor Interface Module (ASIM) is necessary for Non-SPA compliant components to be converted into SPA compliant. Focusing on current ASIM not supporting power hot swap, a SPA-S (SpaceWire) ASIM with power hot swap capability was designed and developed. The FPGA was used to convert device-specific...
It has been shown in previous works that non-uniform sampling and processing is a better scheme than the uniform sampling to sample and process low activity signals. Non-uniform sampling technique generates fewer samples, which means less data to process and lower power consumption. Furthermore, asynchronous logic is known to be data-driven. It proves to be more adapted to the non-uniform sampling...
This article describes the development of the measurement and controlling module that can be controlled through some mobile device (smartphone or tablet) application. The design was influenced by the experiences from the former development and user reactions of similar device that was commercially successful and with good reception. The goal was to create a low-end device that would be also very powerful...
Distributed data acquisition and control systems in large-scale scientific experiments, like e.g. ITER, require time synchronization with nanosecond precision. A protocol commonly used for that purpose is the Precise Timing Protocol (PTP), also known as IEEE 1588 standard. It uses the standard Ethernet signalling and protocols and allows obtaining timing accuracy of the order of tens of nanoseconds...
Carrying out network monitoring tasks remains a continuous challenge, partially because the line rate reaches and exceeds 100 Gbit/s. Besides the increasing data rate, the advent of programmable networks necessitates efficient solutions for supporting packet processing tasks in an adaptive way. Introducing a modification of a protocol or any new protocol in such a flexible infrastructure implies a...
To qualify a System-on-Chip (SoC) for automotive standards, all the interfaces have to be thoroughly checked against the specifications/standards. Sensor protocols which are new to the automotive world don't have the complete range of sensors available as of today for checking the complete features. These sensors operate over a limited range, are not capable of generating all possible frame formats,...
In this paper we present the results of the delay measurements of the Ethernet traffic handled by different Open-Flow switches realized in the NetFPGA cards. We investigated three different software approaches: reference software for Open-Flow on NetFPGA cards, xDPd/ROFL prepared for OpenFlow implementation in NetFPGA cards and xDPD/ROFL library prepared for GNU/Linux cooperating with reference NIC...
Application developers are now turning to field-programmable gate array (FPGA) devices for solutions of small to medium volume due to its post-fabrication flexibility. Unfortunately, the existing upfront intellectual property (IP) licensing model for FPGA based third-party IP cores is economically unattractive. The IP bitstreams in transaction are also vulnerable to cloning, misappropriation and reverse...
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