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3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
The design of efficient router represents a key issue for the success of the network-on-chip approach. This paper presents and evaluates novel router architecture suitable for networks-on-chip (NoC) design. This router offers lowest latency (1 cycle) and allows supporting several adaptive routing algorithms. Latency reduction is obtained by using fast parallel routing (FPR) arbitration that consists...
A special round robin (RR) algorithm has been developed to equalize nickel metal hydride (NiMH) battery packs using a new selective equalizer. This algorithm detects batteries either at a very low state of charge (SOC) or at an extremely high SOC. In this system, a set of electromechanical relays are connected in a matrix to route boost current to the weaker batteries. The relay switching is controlled...
System-on-chip (SoC) design depends heavily on effective reuse of semiconductor intellectual property (IP). Clock distribution has become a problem for integrating IP cores into a single synchronous SoC, because of different clock delays in the IP cores. We propose an on-chip clock-tuning circuit, which enhances design flexibility. Programmable delays are inserted in the clock distribution network,...
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