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Modular polynomial multiplication is the most computationally intensive operation in many homomorphic encryption schemes. In order to accelerate homomorphic computations, we propose a software/hardware (SW/HW) co-designed accelerator integrating fast software algorithms with a configurable hardware polynomial multiplier. The hardware accelerator is implemented through a High-Level Synthesis (HLS)...
In recent years, more and more multimedia data are generated and transmitted in various fields. So, many encryption methods for multimedia content have been put forward to satisfy various applications. However, there are still some open issues. Each encryption method has its advantages and drawbacks. Our main goal is expected to provide a solution for multimedia encryption which satisfies the target...
The H.264 Advanced Video Coding (H.264/AVC) standard is considered to be the most commonly used format for video compression. Although it supports a very broad applications range covering all forms of digital compressed video, the confidentiality of the encoded content needs enhancements. The present work proposes a new selective encryption scheme with multiple security levels. In fact, depending...
In the era of the cloud computing, homomorphic encryption allows remote data processing while preserving confidentiality. Its main drawback, however, is the huge complexity in terms of operand size and computation time, which makes hardware acceleration desirable in order to achieve acceptable performance. In this paper, we present a flexible modular polynomial multiplier implemented through a high-level...
In this paper we present the design considerations of lightweight encryption algorithm. Our aim is to demonstrate how to achieve lightweight block ciphers efficient software performance for low-resource embedded devices. Several lightweight block ciphers are proposed; we selected the most recent and suitable for low-resource embedded systems such as RFID tags. In this work, we analyzed the software...
In recent years, video compression has emerged as an effective technique to reduce spatial and temporal redundancy in video sequence. Temporal redundancy reduction deals with motion estimation (ME) and motion compensation (MC) algorithm with the matching technique to produce the next encoded video frame with motion vector. Motion estimation is the process of determining the movement of blocks between...
Due to their multiresolution signal decomposition, wavelet analysis has shown great success in the analysis of signals such as image processing and video coding. The recent progress in 3D spatio-temporal wavelet video coding led to the emergence of a new generation of scalable video schemes. In fact, much attention has been given to t+2D analysis where temporal redundancy is first exploited through...
No cloning distinguishes the quantum cryptography. Buzek and Hillery have developed a universal quantum cloning machine that allows providing two copies of an arbitrary qubit state with the same accuracy independently of the input-state. The fidelity has been used as a criterion to characterize the cloning. It was found that this parameter can achieve 0.85 for special subsets of quantum states, i...
Motion estimation is the process of determining the movement of blocks between adjacent video frames by which image information is assessed for similarities that can be reused in subsequent frames. However, computational complexity and resource sharing of the motion estimation algorithm poses great challenges for real time applications. Fast search algorithms emerged as important search technique...
Correlation power analysis is the well-known attack against cryptographic modules. An attacker exploits the correlation between the power consumed by a device and the data being processed. In the present paper, we present the experimental procedure of correlation power analysis using three different devices: FPGA, ASIC and a microcontroller. Results show that the power model used to calculate hypothetical...
In recent years, as SoC design research is actively conducted, a large number of IPs are included in one system through network on chip. The real effort and time in using NoC is spent in developing network interfaces (NI) for connecting cores to the NoC. The area and power of NIs should be small and its latency must be kept as low as possible. To reduce power dissipation NIs, we suppose to employ...
The intrusion based on Bužek-Hillery universal quantum copying machine (UQCM) is investigated. A major problem to the eavesdropper Eve is how to choose the intrusion parameters required by the copying machine in order to take out the maximum of information on the transmitted qubits. In the present paper, only the isotropic cloning is considered. The degree of intrusion is evaluated by means of the...
Network on Chip is an efficient on-chip communication architecture for SoC architectures. It enables the integration of a large number of computational and storage blocks on a single chip. The router is the basic element of NoC with multiple, connecting to other router and to a local IP core. This router architecture can be used later for building a NoC with standard or arbitrary topology with low...
The ocular fundus image can provide information on pathological changes caused by local ocular diseases and early signs of certain systemic diseases, such as diabetes and hypertension. Automated analysis and interpretation of fundus images has become a necessary and important diagnostic procedure in ophthalmology. The extraction of blood vessels from retinal images is an important and challenging...
The implementation of a high-performance network-on-chip (NoC) requires an efficient design of the network interface (NI) unit that connects the switched network to the IP cores. In this paper, we present a two novel pipelined NI architecture between IPs and router of NOC. These network interfaces allow system designers to send data from IPs to NOC, and vice versa with low latency. We present how...
Cellular automata (CA) have been accepted as a good evolutionary computational model for the simulation of complex physical systems. They have been used for various applications, such as parallel processing computations and number theory. In this paper, we studied the applications of cellular automata for the modular multiplications; we proposed two new architectures of multipliers based on cellular...
Positions estimation from Time of Arrival (TOA), Time Difference of Arrival (TDOA), and Angle of Arrival (AOA) measurements are the commonly used techniques. These approaches use the location parameters received from different sources and they are based on intersections of circles, hyperbolas, and lines, respectively. The location is determined using standard complex computation methods that are usually...
Transaction level modeling (TLM) has become an accepted and well supported paradigm that is intended to create hardware designs at high abstraction levels. In this paper, we present a methodology that targets the verification of SystemC transaction level models using runtime monitoring. Aspect-oriented programming (AOP) techniques are exploited to handle the high-level TLM features in an automated...
Transaction level modeling (TLM) is increasingly being adopted to describe hardware designs at high abstraction levels. This paper proposes a framework that targets the assertion-based verification (ABV) of SystemC transaction level models during simulation. Aspect-oriented (AO) mechanisms are exploited to write temporal properties that fit TLM requirements. No modifications are needed in the design's...
The paper presents a performance evaluation of MIC@R router for Networks-on-Chip (NoC) design. Its architecture offers lowest routing latency (1 cycle) and allows supporting several adaptive routing algorithms. The proposed router architecture is implemented in ASIC technology and evaluated in 2D Mesh networks with four routing schemes: Deterministic, Fully Adaptive (FA), Proximity Congestion Awareness...
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