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The paper presents a performance evaluation of MIC@R router for Networks-on-Chip (NoC) design. Its architecture offers lowest routing latency (1 cycle) and allows supporting several adaptive routing algorithms. The proposed router architecture is implemented in ASIC technology and evaluated in 2D Mesh networks with four routing schemes: Deterministic, Fully Adaptive (FA), Proximity Congestion Awareness...
The paper presents a design and implementation of router architecture suitable for Networks-on-Chip (NoC) design. This architecture offers lowest routing latency (1 cycle) and allows supporting several adaptive routing algorithms. Latency reduction is obtained by using Fast Parallel Routing (FPR) arbitration that consists in parallel processing and in one stage the routing decisions and arbitration...
The design of efficient router represents a key issue for the success of the network-on-chip approach. This paper presents and evaluates novel router architecture suitable for networks-on-chip (NoC) design. This router offers lowest latency (1 cycle) and allows supporting several adaptive routing algorithms. Latency reduction is obtained by using fast parallel routing (FPR) arbitration that consists...
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