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The traditional hardware description languages (VHDL and Verilog) is not suitable for system-level modeling and Hardware Software Codesign, while the SystemC language is more suitable than the traditional HDL language for system-level modeling. This paper describes the packet processing engine(PPE) characteristics of XDNP network processor, analyze the advantage of system-level modeling in SystemC...
Network-on-Chip (NoC) is considered to be a promising approach to implement many-core systems and a large number of on-chip router optimization studies have been proposed. In this paper, we propose to dynamically adjust link-width of each port on a router optimized to spatially biased traffic. Different from the previous No Coptimization approaches, in which the optimization is almost performed in...
Statistical data from many application fields confirm that SoC products implemented in modern deep submicron technologies are getting more and more susceptible to transient errors. Although thorough and comprehensive understanding of the services that SoCs provide is the key to systematic development, designers no longer can ignore the emerging reliability issues. In fact, proper actions should be...
This article presents a study of the impact of packaging on the memory and power walls, in the context of application properties. The analysis is supported by characterizations of 130 hardware designs spanning 30 years, along with both microarchitectural simulation and actual-hardware performance counter measurements of 25 applications. It is shown that if trends in supply pin count (growing as the...
Graphics Processing Units (GPUs) are becoming increasingly important in high performance computing. To maintain high quality solutions, programmers have to efficiently parallelize and map their algorithms. This task is far from trivial, leading to the necessity to automate this process. In this paper, we present a technique to automatically parallelize and map sequential code on a GPU, without the...
Future manycore Systems-on-Chip will integrate tens or even hundreds of cores. Tiled architectures have come to the focus of research and industry. Such platforms integrate processing cores in clusters and connect those ‘tiles’ with a global interconnect. Message passing programming models are favored to program such complex distributed memory systems. A significant performance overhead is involved...
Sparse Matrix Vector-Multiplication is an important operation for many iterative solvers. However, peak performance is limited by the fact that the commonly used algorithm alternates between compute-bound and memory-bound steps. This paper proposes a novel data structure and an FPGA-based hardware core that eliminates the limitations imposed by memory.
This paper presents a micro-architectural feature in a processor's datapath to support the C language's runtime environment. A hardware accelerator for C function calls was embedded in a processor core and its impact on area and performance was evaluated. Results show that the accelerator offers a performance improvement in several different processor configurations. The performance gain depends on...
Heterogeneous Multi-Processor System-on-Chips (HMPSoCs) offer an attractive alternative to homogeneous systems to achieve the increasing requirements of modern media-processing applications. Such systems take advantage of the heterogeneity of their processing units (RISC vs. VLIW) combined with efficient memory architecture and a specific communication infrastructure. However, the complexity of such...
Testing embedded microprocessors at mission time is nowadays a requirement in many SoC applications. In this paper, we introduce a methodology where the detection of operational faults is performed while the normal operations are temporarily suspended, by means of an ad-hoc HW module connected to the address, data and control buses of the microprocessor. This module behaves as a peripheral towards...
This paper presents a mechanism to decrease the congestion on TDM networks handling both Best Effort and Guaranteed Throughput traffic. The mechanism consists of an algorithm which gives an optimal Time Slot to begin transactions between source and destination, thus maximising the probability of successfully reserving a path through the network, to guarantee Quality of Service for the streaming traffic...
During recent years the dependability and security requirements of system-on-chip (SoC) designs have increased tremendously. Both, dependability and security, domains are concerned with operational faults of a random or intentional nature. In former case random faults e.g. caused by radiation or degradation effects could lead to execution errors with possible dramatic results. The security domain...
We consider the challenges in writing efficient code for ePUMA, a novel domain-specific heterogeneous multicore architecture with SIMD DSP slave cores, multi-banked on-chip vector register files for parallel access and configurable permutation hardware that decouples memory access from computation. Suitable data layout in memory and in vector registers, combined with using ePUMA's powerful addressing...
In this paper, an overview of reconfigurability is presented with some design recommendations. Besides, a design flow of a Reconfigurable System on Chip (RSoC) is studied for an application case: the implementation of two different controllers on Multiprocessor SoC (MPSoC) architecture using the FPGA Virtex-II Pro. A runtime partial reconfiguration is adopted to switch between them. A predictive internal...
Automatic Number Plate Recognition (ANPR) systems have become an important tool to track stolen car, access control and monitor the traffic. The fundamental requirements of an ANPR system are image capture using an ANPR camera, and processing of the captured image. The image processing part, which is a computationally intensive task, includes two stages i.e. plate localisation and character recognition...
To meet performance requirements, streaming applications have been mapped to Multi-Processor System on Chip (MPSoC). The Kahn Process Network (KPN) paradigm is sufficient when dealing with pipeline parallelism, but such point-to-point channels are impractical in the presence of massive task farm parallelism. Multi Writer Multi Reader (MWMR) channels generalize KPN in such a way that multiple writers...
The reuse of predefined Intellectual Property (IP) can shorten development times and help the designer to meet time-to-market requirements for embedded systems. Using FPGA IP in a proper way can also mitigate the component obsolescence problem. System migration between devices is unavoidable, especially for long lifetime embedded systems, so IP portability becomes an important issue for system maintenance...
Education of embedded systems is essential for Computer Science and Electrical Engineering students. However, traditional courses of embedded systems in the university cannot satisfy all industrial requirements anymore due to the extreme wide applicable area of embedded systems nowadays. In this article, we propose a series of short courses for learning embedded systems. Three hardware platforms focusing...
As today's consumer electronics get increasingly portable and ubiquitous, rising complexity succeeds to more functionalities integrated. Market dynamics and competitiveness further squeeze the time-to-market requirement, consequently pushing system designers to the very throughout consideration during the development process. Traditional development approaches could not satisfy with such compact demands...
Aiming at improving the flexibility and reducing the cost of SOC system design, the design of configurable IP core is prerequisite. In this paper, we mainly design a scalable configurable IP core and its configurable interface circuit. We call it FDP (FuDan Programmable) Configurable IP Core. This IP Core meets the requirement of configuration and scalability. Based on FDP Configurable IP Core, we...
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