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It is well-known that self-stabilized circuits, such as current, voltage and frequency references, are vulnerable to multiple operating points problem. This is also known as the start-up problem. In this paper, we show that the widely used analog building block, namely the op-amp, can suffer from the same problem when performance enhancement feedback is being used. In particular, slew rate enhancement...
This paper presents, we present a novel method for CMOS implementation of programmable gaussian fuzzifier. Utilizing the proposed mechanism, only one transistor is required to control the slope of the generated Gaussian membership function. Comparing to some other works in the literature, the proposed circuit requires lower power consumption as well as low circuit area, which makes this structure...
In this paper, a CMOS biologically expansion/contraction motion sensor and its implementation on $Z$ -motion direction/velocity detection is newly proposed. The first innovation is that the proposed method is inspired from neural vision system of mammalians. The formation of image is based on the principle of biconvex lens geometry. By developing the proposed method, the proposed motion sensor can...
Conventional CMOS technology provides a lot of opportunities in the field of electronics device. But presently, carbon nanotube field effect transistor (CNTFET) is a new technology for the application in the field of electronic device. Due to the limitation of the size of CMOS, CNTFETs are the promising substitute due to its nano scale size. CNTFET also shows the high stability, low power circuit...
After the invention of the MOSFET, continuous scaling of the device is going on as predicted by Moore in 1970. This reduction in device size is giving higher performance in terms of increased speed, lower power consumption at lower cost with greater chip density. At the same time, because of the scaling, the channel length is decreasing continuously leading to short-channel effects (SCE) in nanoscale...
Modulo multiplication forms the basic block of Residue Number System (RNS) based Digital signal processing and cryptographic applications. Several techniques are proposed to concise the computation complexity of the multiplier design. In this paper the area and power efficient modulo 2N multiplier for {2N-1, 2N, 2N+1} based RNS is designed involving Logarithmic Number System (LNS) concept. The divided...
This paper introduces a step forward towards memristor-MOS hybrid circuit to achieve any combinational function. The proposed design is based on reducing the area by replacing the complete pull-down network with just one memristor and one comparator. The concept is then verified using an example of a simple function. Also, a proposed architecture for memristor based redundant multiplier circuit is...
This paper proposes a novel low-power burst-mode clock recovery circuit (CRC) based on analog phase interpolator (PI). Accordingly, we employed a new configuration for PI-based CRC in which a novel architecture is utilized for double-edge triggered sample-and-hold (DT-SH). In the proposed DT-SH one buffer is shared between two single-edge triggered SH (ST-SH) resulting in great reduction of total...
From the past few years a variety of low power adders have been proposed to reduce the overall power consumption of micro-electronic systems. The role of adders are important in almost all fields of engineering and applied sciences. With the help of low power adders, all the other systems which make use of adders may dissipate less power. This study presents a detailed comparison between various low...
This paper proposes a 10-bit linear gamma digital-to-analog converter (DAC) of source driver ICs for large-sized active matrix flat panel displays (AMFPDs). The proposed DAC employs the voltage adder to reduce the area of source driver IC. The voltage adder not only reduces the size of 7-bit DAC to about half by adding the fixed one least significant bit (LSB) voltage but also quickly settles the...
This paper presents two new approximations for the logarithmic and exponential functions. These approximations require only a square rooter function, a scalar function and a constant. Thus, the realization of these functions in current-mode is simple, straightforward and uses less number of transistors. Simulation results obtained using the Tanner simulation software from Tanner EDA in 0.35µm standard...
This paper describes a fine resolution, good linearity, and high throughput time-to-digital converter (TDC), which has realized in 0.18um CMOS technology. Based on a two-channel Vernier delay line (VDL) structure and an asynchronous pipelined readout circuitry, the TDC can achieve a maximum throughput of 500MS/s, a time resolution of 10ps and a total conversion range of 640ps. The proposed architecture...
Dynamic circuits using n-channel multiple-input floating-gate MOS(FGMOS) transistors to realize binary and ternary logic are presented. In binary domino circuits, the n-channel FGMOS transistors are used to replace the nMOS logic block to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a...
An approach towards a high speed current mode SAR ADC is presented. Even though SAR ADCs based on charge redistribution have been significantly improved in efficiency and operating frequency, they are still limited by the settling requirements of the switched capacitor DAC. To overcome this limitation, we propose the use of a current mode SAR ADC incorporating a current steering DAC operating at 2...
In this paper, we have proposed a 4-bit 5-GSample/s flash analog-to-digital converter (ADC) for pulse amplitude modulation (PAM) systems. In order to achieve low-power consumptions, digitalized cells for analogue amplifying are developed in the proposed ADC. Digitalized cells reduce power significantly due to using fewer devices as compared to pure analogue designs. A self-biasing circuit is used...
The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed...
The design of a programmable frequency divider based on a pulse swallow counter is presented to meet the requirement of high speed working. An improved and optimized dual-modulus prescaler which is the core of the divider is proposed for trade-off between high speed and low power. The divider is fabricated in SMIC 0.18μm CMOS process, and the calculation and simulation results indicate its minimum...
The Ultra Low-Voltage (ULV) NAND and NOR gates are presented in this paper. These gates are based on the ULV precharge inverter presented in [11]. We intend to verify the gates' logical expression of NAND and NOR. The inbound precharge logical behaviours of the gate have been previously discussed, and therefore we aim to compare these new NAND and NOR designs to traditional Domino and CMOS logic styles...
The design of a CMOS integrator for offset voltage monitoring in implantable neural stimulation systems is presented. It reduces the risk of electrode dissolution and tissue destruction, which might arise from a residual electrode potential after unbalanced high voltage (HV) stimulation pulses. The integrator therefore requires HV robustness and low power consumption at the same time. Monitoring low...
A Δή all-digital delay-locked loop (ADDLL) is proposed to realize a PVT-insensitive time-to-digital converter (TDC) with enhanced linearity in an all-digital phase-locked loop (ADPLL). With the proposed TDC, poor timing resolution and nonlinearity problems are mitigated, enabling a low cost, low comparison frequency TDC design without using the advanced CMOS technology. A novel digitally-controlled...
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