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This paper presents the design of a novel RF power amplifier (PA) suitable for modern wireless communication systems. The PA employs switching mode class-E topology to exploit its soft-switching property to achieve high efficiency. The use of another class-E stage as a driver of power stage improves efficiency and increases the capability of circuit integration. A new output power control technique...
In the wireless telecommunication systems, for increasing interest in RF switch using Complementary Metal Oxide Semiconductor (CMOS) technology, for high frequency is greatly integrated. In this paper, we use the Hafnium-dioxide material as dielectric substrate for designing a model of CMOS which is used for double-gate MOSFET in DP4T RF CMOS switch. This proposed model is compact and robust as well...
This paper proposes a new active shunt-peaked realization for MOS Current Mode Logic (MCML) based memory element. The circuit proposes the use of active inductors in shunt-peaking of MCML memory element. The technique of shunt-peaking offers a way of enhancing the performance of gates at high speed of operations. The benefit of the proposed circuit is verified by designing and simulating various MCML...
Demand of radio frequency switches using Metal-Oxide-Semiconductor (MOS) technology at high-frequencies for wireless telecommunication system is increasing drastically. This paper presents the results for the development of a cell library that includes the basics of the design parameters for n-MOS transistor and p-MOS transistor to design a RF CMOS switch. The cell library design includes the properties...
This paper presents a low power all-digital phase locked loop (ADPLL) with power optimized digitally controlled oscillator (DCO). In this paper, the power optimization procedure of DCO is proposed for low power ADPLL. The procedure is based on simple equations about relationship between control bits and power dissipation. To validate the procedure, DCO has been designed and fabricated using 0.13μm...
In this paper, a fully integrated CMOS receiver front-end for 2.4-GHz Band IEEE 802.15.4 standard in a 0.18-μm CMOS technology is presented. It is comprised of a low-power CMOS LNA including a common-gate stage with modified input matching and active balanced down-conversion mixer which uses the current bleeding technique and an extra LC filter to improve the noise figure (NF) and conversion gain...
A fully integrated Phase-Locked Loop (PLL) as a clock generator is described in an advanced 32nm CMOS technology. Features include adaptive bandwidth architecture, automatic frequency calibrator (AFC), a sub-1V V/I converter operation, feedback control to minimize charge-pump current mismatch, and a fully integrated loop filter. The whole PLL measures power consumption of 1.6mW when VCO oscillates...
A 2.4GHz receiver front-end with on-chip balun implemented with 0.13um CMOS technology is presented in this paper. Based on direct-conversion architecture, the front-end comprises a two-stage LNA (low noise amplifier) with optimized on-chip transformer and quadrature passive mixer. The gm-boosting technique is employed in 1st stage of LNA to achieve low noise and low current simultaneously. In 2nd...
A novel CMOS temperature sensor embedded in a passive UHF RFID tag is presented. The sensor consists of a temperature-to-current converter, two current-starved ring oscillators and two digital counters. High power consumption band-gap voltage references and traditional ADCs are not used for low power design. Post-layout simulation show that the power consumption is 0.64 μW with a supply voltage of...
This work presents a low noise amplifier (LNA) and mixer for 1558-1578 MHz Global Position System (GPS). The LNA uses cascode structure to eliminate the Miller effect. Also the next stage, the double-balanced Gilbert cell mixer is accomplished for good performance such as isolation. We suggest a Single-Differential LNA mode which has enough gain and two differential outputs. The LNA and Mixer are...
This work presents the design of a Low Noise Amplifier in 0.35 μm CMOS technology from Taiwan Semiconductors. A single ended cascade configuration with inductive degeneration followed by a common source configuration is used. The circuit is designed in Cadence and employs feedback technique along with the use of a PMOS as a feed forward distortion canceller to further improve linearity. At 900 MHz,...
This paper demonstrates a highly integrated transceiver for 802.15.4, consuming a dc power of 18 mW and 22.3 mW in the Tx and Rx mode respectively. The gm boosted LNA shares the dc current with mixer, complex filter uses transistorized biquads, Limiting Amplifier and RSSI chain uses two local loops to save dc power. In the Tx, 2-point direct FSK modulation using normal sized varactors are used in...
A novel 1.575 GHz CMOS common-mode replica compensated LC voltage-controlled oscillator with enhanced power supply rejection (PSR) is introduced for global position system (GPS) system-on chip application. In order to improve the PSR and reduce the power consumption, additional regulating circuit with feed forward and feedback amplifiers are implemented using transconductance stages with common-mode...
A low-energy 2.4GHz RF transceiver supporting 1Mb/s Gaussian Frequency-Shift Keying modulation and designed to run on a 1.5V battery is implemented in a standard 0.18μm CMOS technology. The integrated DC-DC converter can provide up to 100mA to an external load besides the current required by the transceiver. The transmitter current at 0dBm nominal output power is 11.9mA. The receiver draws 11.4mA...
This paper designs and implements an direct up-conversion mixer based on RF CMOS process, which can be used in the up-link radio frequency (RF) front-end of a 2.4 GHz wideband wireless system such as multimedia wireless sensor network (WSN). Firstly, Gilbert cell-based double-balanced structure is adopted in this design, which can effectively suppress the feed-through of the local oscillator (LO)...
This study was initiated to design a low noise amplifier (LNA), which could work with ultra low voltage of 0.5V and was optimized for WSN application using SMIC 0.13 μm RF-CMOS technology. The topology of differential inductance degenerated folded cascode based on power-constrained simultaneous noise and input matching (PCSNIM) technique was adopted. Chosen circuit demonstrated a power gain of 16...
A fully integrated double frequency differential LC voltage controlled oscillator (VCO), used in the frequency synthesizer of 2.4GHz IEEE802.15.4/ZigBee Wireless Sensor Network (WSN), is designed and implemented based on TSMC 0.18μm RF CMOS process with low power dissipation and wide tuning range. The core circuit adopts complementary differential negative resistance LC oscillator structure and is...
A fully integrated double frequency differential LC voltage controlled oscillator (VCO), used in the frequency synthesizer of 2.4GHz IEEE802.15.4/ZigBee Wireless Sensor Network (WSN), is designed and implemented based on TSMC 0.18 μm RF CMOS process with low power dissipation and wide tuning range. The core circuit adopts complementary differential negative resistance LC oscillator structure and is...
A nano-power power-on-reset (POR) circuit for passive RFID tag is presented in this paper. It is applied to a passive UHF C1G2 RFID tag ICs fabricated in a 90-nm CMOS technology. Measurement results confirm that the generated POR pulse signal is accurate and reliable due to the proposed hysteresis-comparator structure and power-off auto-discharging path. Moreover, the POR circuit consumes 150-nA quiescent...
This paper introduces the way to minimize the phase noise of VCO using LC 2nd harmonic wave filtering technology, and fulfills the design of 1.8GHz low phase noise, low power consumption VCO with TSMC RF CMOS 0.18μm standard technique. The tuning range reaches 560MHz, phase noise - 121dBc/ Hz@1 MHz. The method, introduced in the paper to minimizing phase noise of VCO, puts forward a valuable reference...
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