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Scan architectures with compression support have remedied the test time and data volume problems of today's sizable designs. On-chip compression of responses enables the transmission of a reduced volume signature information to the ATE, delivering test data volume savings, while it engenders the challenge of retaining test quality. In particular, unknown bits (x's) in responses corrupt other response...
In prior work, profiling-based chain diagnosis methodologies were developed. This paper discusses the challenges associated with profiling-based chain diagnosis in the production test environment with limited failure buffer capacity on tester. We propose the following two pattern masking application flows to enhance diagnosis resolution in this scenario: (1) generic pattern masking and (2) adaptive...
This paper presents a Design-for-Test approach for digitally-assisted analog IPs in automotive applications. It adopts an on-chip measurement architecture based on the IEEE 1500 Standard to deal with analog test. The architecture is modular-based and scalable, suitable for parametric DC and delay measurements, and capable of executing concurrent on-chip measurements. The design implementation is simple,...
We present a new compactor architecture for extreme compaction of test responses with a high percentage of x-values. The test response data is compacted into a single, 1-bit wide bit stream. A major contribution of this work is a new technique to efficiently load x-masking data into a masking logic. A method eliminating the need for explicit mask control signals using ATE timing flexibility is also...
A built-in self-test (BIST) for testing high speed source-synchronous memory interfaces has been designed using 0.18-μm TSMC process. To overcome limitations of the resolution and the accuracy in low-cost automated test equipment (ATE), a cycle-by-cycle controllable embedded pattern generator in the proposed BIST scheme is presented to specify performance-related I/O parameters. Using this method,...
This study presents an empirical analysis of the effects on correlation of the site-to-site transport of ATEs. Four correlation scenarios are presented with permutations of calibration/non-calibration of the testers. The results show that the least number of uncorrelated tests are encountered when there is calibration at the reference tester site, with or without calibration on the target site. Also,...
With the growth of memory capacity and density, test cost and yield improvement are becoming more important. To increase yield of memory, redundancy analysis (RA) which analyzes the faults in memory is essential. However, the time for finding solutions to repair memories with faulty cells is very huge because most RA algorithms for automatic test equipment (ATE) are based on a tree structure. To reduce...
In this paper, the test methods of the Hydraulic Test-bed of Cylinder are researched, such as hydraulic cylinder stroke test, buffer test, high temperature test, internal leakage rate test ultrahigh pressure test. The measurement and control system is made up by industrial control computer, programmable logical controller, data acquisition card, analog control card and high precision sensors. The...
The basic principle of double ramping test method involves ramping two voltages at different slew rate measuring the threshold and calculates the delay time at the same test setup. The test method available at present are performed in two separate stages which cause a longer test time and require different type of instrument, example using analog and high speed digital instruments. Analog instrument...
This paper describes the evolution of procedures to protection relays performance testing. In the early days, the measurement and calibration of relays were made by analog devices and instruments that basically provided the steady-state tests. In the 70's came the electronic test equipment. With the passage of time have evolved, providing a full range of dynamic tests. With technological advances,...
The following topics are dealt with: low-cost ATE in the GHz era; microprocessor test including at-speed learning; DFT advances; ATPG techniques; post-silicon validation; 3D test; memory online test and fault tolerance; RF test techniques; scan compression; detecting and understanding defects; parallel TG and fault simulation and diagnostic TG; DFM and yield-learning via design and data analysis;...
We will demonstrate the effectiveness of power supply active compensation techniques in mixed signal device performance testing. Read channel speed sorting for data storage SOCs is used to illustrate how we minimize the power transient effect in ATE test, where read-channel current draw varies drastically between different mission-modes and power-saving-modes. These active compensation ideas are critical...
Testing multiple device functions in parallel can yield significant test time and cost of test reductions. This paper discusses the planning process and algorithms required to realize an efficient and achievable concurrent test plan.
Standardization of data formats is one key factor in enabling automation of a process. The IEEE P1450 family of standards has made significant contributions to standardization of test generation and data transfer. Currently there is no standard for test flow specification within STIL, and the test generation is mostly a manual process which is tedious, error prone and leads to suboptimal flows. IEEE...
A new implementation of EVM measurement has been developed in a production test environment using an FPGA-based DSP processor within an ATE test solution. The focus of interest is in identifying key areas of the DSP that affect measurement quality and optimizing their execution on an FPGA to increase measurement accuracy, precision, repeatability, and reduce test time. This approach defines a real-time...
In this article, an accurate and low-cost clock delay generation system integrated in an automated test equipment (ATE) environment is presented. The input to this system is entirely digital and is driven by a single clock, which can be programmed from the ATE High Speed Digital (HSD) unit. Moreover, the digital input patterns can easily be generated in software off-line; hence, making this system...
This paper describes a drastically downsized RF test module with multiple resources and high throughput for RF ATE systems. The major factor in downsizing is RF circuit technology in the form of RF functional systems in package (RF-SiPs), making it possible to construct RF front-end without both RF cables and RF connectors. Besides the above downsizing, high-speed RF switching operations are also...
Test data compression is widely employed in scan designs to tackle high test data volume and test time problems. Given the number of scan-in pins available in the ATE, architectural decisions regarding the number of internal scan chains directly impact the compression level attained. While targeting an aggressive compression level by increasing the number of internal scan chains would reduce the test...
This paper describes the timing skew compensation technique using the digital filter with our novel linear phase condition. First we describe the digital filter which can set its group delay with the arbitrary fine time resolution while it maintains the linear phase characteristics; the conventional linear phase digital filter can set its group delay with the time resolution of a half of the sampling...
We have developed a novel timing vernier for a high integration CMOS timing generator of Automatic Test Equipment (ATE). To reduce area and power, the proposed timing vernier utilizes the charge injection architecture. An 893ps span, 7ps resolution timing vernier is fabricated in a 0.18 μm CMOS process. We achieved a linearity error of 4.2ps pp without calibration. The timing vernier occupies an area...
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