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In this study, we use the standard TSMC 0.35 μm 2P4M process to design CMOS-MEMS probe chip. MEMS technology involves the following steps such as lithography process, electroless nickel (EN) plating process, grinding process and dry etching process. The probe chip has through silicon via (TSV) package structure, and the combination of CMOS process within the multi-layer interconnections, which could...
In this paper, we present our vision of a highly scalable arrayed biochemical sensor platform. This platform combines the advantages of refined and entrenched technologies like top-down integrated circuit fabrication and clinical assays with emerging technologies like three-dimensional stacking and label-free sensing. We demonstrate fabrication concepts and preliminary sensing results on ovarian cell...
Three dimensional silicon integration technologies are gaining considerable attention as the traditional CMOS scaling becoming more challenging and less beneficial. The advanced packaging solutions based on thin silicon carrier are being developed to interconnect integrated circuits and other devices at high densities. A key enabling technology element of the silicon carrier is through silicon via...
This paper demonstrates a dry heterogeneous integration process for embedding CMOS chips into a partially-complete MEMS silicon wafer. By using standard IC processing, we create passive alignment structures in backside cavities on the MEMS wafer. The precision dry assembly utilizes front-to-front registration, removing the need for sidewall slope control of the backside Deep Reactive Ion Etch (DRIE)...
We have developed a new 3-dimensional (3D) Wafer-to-Wafer stacking technology in which each wafer was stacked one after another, using a unique Through Silicon Via (TSV) fabricated by wet etching technology and surface-micro bump on the lower wafer. Our Wafer-to-Wafer stacking method use a direct connection between backside TSVs of an upper wafer and micro-bumps of a lower wafer. This interconnection...
One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach maximizes transducer sensitivity by minimizing parasitic capacitances and ultimately improves the signal to noise ratio. Additionally, due to physical size limitations required for catheter based imaging devices, optimization of area occurs when the...
This work describes the development of hybrid circuits composed of silicon-based molecular electronic devices and traditional CMOS technology. In the development of these circuits, we first fabricated individual CMOS-compatible molecular electronic devices and established their effectiveness. We then designed and used traditional VLSI tools to layout a hybrid circuit that includes CMOS for the on-chip...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
CMOS molecular (CMOL) circuits promise great opportunities for future hybrid nanoscale IC implementation. In this paper, a novel three dimension (3D) architecture of CMOL circuit is introduced. It eliminates the special pin requirement, enabling feasible fabrication. It also doubles the density of nanowires of the original CMOL circuit, while providing similar operation performance. This work significantly...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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