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The tendency for low energy consumption in systems-on-chip results in a need for memories operating in the near- and sub-threshold regions. This paper gives a comparative study of Static Random Access Memory (SRAM) bitcells working under Ultra-Low Voltage in 32nm CMOS. A new 10T SRAM bitcell is then proposed and features low leakage current. It is capable of operation under ULV (∼300mV) and allows...
We propose a Loadless 4T SRAM cell using degenerately doped source (DDS) p-channel In0.53Ga0.47As Tunnel FETs (TFETs) as dual purpose access/load devices and low leakage steep sub-threshold n-channel TFETs as drive devices. A Loadless 4T CMOS SRAM cell has the requirement that the leakage current of the PMOS access transistors should be larger than the leakage current of the NMOS drive transistors...
Transistor scaling has enabled more memory to be embedded on-chip to accelerate large scale applications. However, increased leakage current in scaled technologies resulted in higher standby power consumption in volatile memories. Nonvolatile memories have been researched and developed as solutions to these problems. However, non-volatile memories such as Flash or magnetic spin torque memories require...
This paper presents an improved circuit design of low power 1-bit full adder circuit. The circuit is designed and implemented based on top-down approach using total number of 10 transistors, thereby, known as 10-T cell. After simulation of the circuit, a clear view of the circuit performance, in terms of power, delay, area was studied. The performance of the proposed circuit was compared with other...
Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This paper presents a tri-modal switch cell that enables implementation of multimodal power gating, including active, data-retentive drowsy, and deep sleep modes. A circuit realization and design methodology are presented that allow...
Based on the observation that dynamic occurrences of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor SRAM cell (4T SRAM cell) for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. Novel...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
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