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Most existing concepts for hardware implementation of reversible computing invoke an adiabatic computing paradigm, in which individual degrees of freedom (e.g., node voltages) are synchronously transformed under the influence of externally- supplied driving signals. But distributing these "power/clock" signals to all gates within a design while efficiently recovering their energy is difficult...
The feasibility of using commercial CMOS processes for implementing scalable cryogenic control electronics for universal quantum computers is investigated. Using a systems engineering approach, we break the system down into sub-systems and model the individual components down to transistor level. First results for area demand and power consumption indicate that even with a standard CMOS process, it...
The article issue is the enterprise information protection within the internet of things concept. The aim of research is to develop arrangements set to ensure secure enterprise IPv6 network operating. The object of research is the enterprise IPv6 network. The subject of research is modern switching equipment as a tool to ensure network protection. The research task is to prioritize functioning of...
Software-defined networks (SDN) are vulnerable to most of the attacks that traditional networks are vulnerable to. In addition, SDN has introduced new vulnerabilities through its unique architecture such as those related to the southbound and northbound controller interfaces. In this paper, we introduce a lightweight flow-based Intrusion Detection System (IDS) that periodically gathers statistical...
Underwater sensor networks are bounded by data sensing, transmitting, and forwarding limitations. The transmitting of large volumes of data can require a large amount of time and power. This has led researchers to focus on the new technology of underwater computing systems, in which information is extracted under the water using embedded processors via data mining and/or data compression. In this...
This paper describes a half-semester module in an Introduction to Engineering course that uses microelectronics technology to introduce students to basic ECE concepts and engineering design. The module uses CMOS integrated circuit technology as a vehicle for introducing basic concepts including voltage, current, and logic levels while also providing students with perspective on how integrated circuits...
Integrated circuit (IC) camouflaging is a layout-level technique that hampers reverse-engineering attacks. In one embodiment of camouflaging, layouts of different Boolean gates are designed to look alike by using a combination of true and dummy contacts. The security of IC camouflaging using dummy contacts depends on an attackers inability to determine whether a contact is true or dummy. The layouts...
An Arithmetic logic Unit (ALU) is used in arithmetic, logical function in all processor. It is also an important subsystem in digital system design. Arithmetic Logic Unit (ALU) is one of the most important components of any system and is used in many appliances like calculators, cell phones, and computers. A 32-bit ALU was designed using Verilog HDL with the logical gates such as AND and OR for each...
There has been a recent rapid increase in the number of Internet of Things (IoT) devices, providing a wide range of services for smart homes such as surveillance cameras, smart lighting, and door locks that can be remotely accessed and controlled. User mobility makes static security mechanisms, such as usernames and passwords, tedious to use. In this paper, we introduce a context-aware authentication...
One of the crucial challenges in the recently emerging Internet of Things (IoT) applications is how to handle the massive heterogeneous data generated from a large number of resource-constrained sensors. In this context, cloud computing has emerged as a promising paradigm due to its enormous storage and computing capabilities, thus leading to the IoT-Cloud convergence. In such a framework, IoT devices...
Memristor is a two-terminal nanodevice that has recently attracted the attention of many researchers due to its simple structure, non-volatility behaviour, high-density integration, and low-power consumption. This paper presents and evaluates a novel binary multiplier composed of memristive devices and nanowire crossbar arrays. Using the proposed multiplier instead of usual digital circuits, the number...
Quantum computing is rapidly evolving especially after the discovery of several efficient quantum algorithms solving intractable classical problems such as Shor's factoring algorithm. However the realization of a large-scale physical quantum computer is very challenging and the number of qubits that are currently under development is still very low, namely less than 15. In the absence of large size...
A major hurdle to the deployment of quantum linear systems algorithms and recent quantum simulation algorithms lies in the difficulty to find inexpensive reversible circuits for arithmetic using existing hand coded methods. Motivated by recent advances in reversible logic synthesis, we synthesize arithmetic circuits using classical design automation flows and tools. The combination of classical and...
Quantum computers may revolutionize the field of computation by solving some complex problems that are intractable even for the most powerful current supercomputers. This paper first introduces the basic concepts of quantum computing and describes what the required layers are for building a quantum system. Thereafter, it discusses the different engineering challenges when building a quantum computer...
We survey recent strides made towards building a software framework that is capable of compiling quantum algorithms from a high-level description down to physical gates that can be implemented on a fault-tolerant quantum computer. We discuss why compilation and design automation tools such as the ones in our framework are key for tackling the grand challenge of building a scalable quantum computer...
Current techniques for formally verifying circuits implemented in Galois field (GF) arithmetic are limited to those with a known irreducible polynomial P(x). This paper presents a computer algebra based technique that extracts the irreducible polynomial P(x) used in the implementation of a multiplier in GF(2m). The method is based on first extracting a unique polynomial in Galois field of each output...
In today's world power dissipation is one of the major concern as the complexity of the chip is increasing and more devices are being integrated on a single chip. Thus this high density of chip and increased power dissipation demands for better power optimization methods. Reversible logic is one of the method to reduce power dissipation. Reversible computing has a wide number of applications in areas...
Today's rapid advances in the physical implementation of quantum computers demand for scalable synthesis methods in order to map practical logic designs to quantum architectures. We present a synthesis algorithm for quantum computing based on k-LUT networks, which can be derived from Verilog netlists using state-of-the-art and of-the-shelf mapping algorithms. We demonstrate the effectiveness of our...
Galois field (GF) arithmetic is used to implement critical arithmetic components in communication and security-related hardware, and verification of such components is of prime importance. Current techniques for formally verifying such components are based on computer algebra methods that proved successful in verification of integer arithmetic circuits. However, these methods are sequential in nature...
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