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Currently, there are many tools that modify the program code of the compiled protected modules. The authors of the considered tools do not publish technique of embedding their protection system and any proofs of their tools' algorithm correctness. This article describes the technique of program module modification with algorithm preservation for the subsequent embedding a protection system. The article...
We define some of the programming and system-level challenges facing the application of quantum processing to high-performance computing. Alongside barriers to physical integration, prominent differences in the execution of quantum and conventional programs challenges the intersection of these computational models. Following a brief overview of the state of the art, we discuss recent advances in programming...
Physical design tools must handle huge amounts of data in order to solve problems for circuits with millions of cells. Traditionally, Electronic Design Automation tools are implemented using Object-Oriented Design. However, using this paradigm may lead to overly complex objects that result in waste of cache memory space. This memory wasting harms cache locality exploration and, consequently, degrades...
Making the data plane of a SDN flexible enough to satisfy the various requirements of heterogeneous IoT applications is very desirable for Software Defined IoT (SD-IoT) networking. The network device having programmable data plane provides an ability to add new packet and data processing procedures dynamically to the IoT applications. Previously proposed solutions for adding programmability to the...
This paper presents the system that allows SEFI modelling by means of injecting upsets in different microcontroller memory blocks, carrying out its functional control and detect the moment when SEFI occurs. Test setup was developed on the basis of National Instruments PXI modular equipment and LabVIEW software. Developed fault injection system was tested on PIC17 microcontroller. The comparison between...
In the process of multi axis machine tool, sometimes it is necessary to switch between the rotating spindle and the rotary feed shaft. In order to satisfy the request mentioned above, this article makes a brief introduction to the upper software and analyzes the control principle of spindle by using PMAC, combined with that, a method to deliver the automatic switching function between spindle mode...
This paper presents a Controller Area Network (CAN) communication system in the Field-Programmable Gate Array (FPGA), which is Xilinx Artix-7. Hardware circuits and the software flow char are described in detail. The reusable IP (Intellectual Property) technology is used in FPGA as the core controller. In addition, the CAN communication system is implemented by System-on-a-Programmable-Chip (SOPC)...
In Systems Biology, Boolean models are gaining popularity in modeling and analysis of qualitative dynamics of gene regulatory mechanisms. With the development of advanced high-throughput technologies, the availability of experimental data on gene-gene, gene-protein interactions is ever increasing. Consequently, modern Boolean models are increasing in size and complexity. Software simulation of Boolean...
Security is a major issue nowadays for the embedded systems community. Untrustworthy authorities may use a wide range of attacks in order to retrieve critical information. This paper introduces ARMHEx, a practical solution targeting DIFT (Dynamic Information Flow Tracking) on ARM-based SoCs (e.g. Xilinx Zynq). Current DIFT implementations suffer from two major drawbacks. First, recovering required...
This paper presents a technique to integrate wireless field devices using WirelessHART and ISA100.11a technologies into a condition monitoring system based on Wonderware InTouch software. The proposed integration brings the data from a field site with digital multi-device networking for automatic data collection to support the condition monitoring of instruments or smart connected equipment in preparation...
Modern ASIC and FPGA based embedded products use model based design, in which both hardware and software are developed in parallel. Previously HW was completed first and the information handed over to SW team, typically in the form of register tables. The information was even manually copied to SW code, making any changes error-prone and laborious. IP-XACT is the most feasible standard to model HW...
The design of today's systems on chip (SoC's) raises difficult issues, in particular regarding verification. In their early design phases, hardware/software embedded systems are commonly described as ESL (Electronic System Level) models, such that their functional and transactional behavior can be analyzed by simulation. To enhance this validation process, we have previously developed a framework...
Flash memory-based storages are used in a wide range of systems from small mobile devices to large-scale system servers. The performance demand from applications and the technology of flash memory vary widely from one system to another, making it difficult to design a universal flash memory scheduler for all systems. In this paper, we present a framework for efficient and flexible flash memory scheduling...
A central processing unit (CPU) and peripheral devices are discussed for which all data processing and data transfer is uniquely time tagged using a timestamp generated by the embedded processing system master clock. The Time Aware Processor (TAP) introduces time into the processor computing language to relate data to temporal events, including the processors own internal functions.
Reliability evaluation is a critical task in computing systems. From one side, the results must be accurate enough not to under-or over-estimate the overall system reliability (thus either resulting in a non-reliable system, or a system for which too expensive solutions have been adopted). On the other side, the time required for the analysis should be kept at the minimum. This paper presents some...
Earlier P2020 SEE data are compared and expanded to a recent die revision, significantly increasing samples tested by protons by five devices, and by heavy ions by five devices. Earlier tested SEE types are found to be fairly similar in register, L1 cache, L2 cache, and CPU crashes. New test methods give SEE performance for the flash memory controller, watchdog circuit, and a built-in Ethernet port...
The Low Frequency Aperture Array (LFAA) component of the Square Kilometer Array (SKA) involves the processing of 218 signal chains, which will be performed on custom FPGA boards, the Tile Processing Module (TPM). These TPMs, as well as firmware running on them, need to be managed, monitored and controlled by the rest of the system. This requires access to on-board devices and registers on running...
An important part of software engineering (SE) research is to develop new analysis techniques and to integrate these techniques into software development practice. However, since access to developers is non-trivial and research tool adoption is slow, new analyses are typically evaluated as follows: a prototype tool that embeds the analysis is implemented, a set of projects is identified, their revisions...
Effective software defences against errors created by fault attacks need to anticipate the probable error response of the target micro-controller. The range of errors and their probability of occurrence is referred to as the Fault Model. Software defences are necessarily a compromise between the impact of an error, its likelihood of occurrence, and the cost of the defence in terms of code size and...
This paper discourse about a low area elliptical curve cryptographic processor with high performance is implemented. The architecture proposed comprises of a full precision multiplier with two staged segmented pipelining to lessen the clock cycles used by avoiding data dependency. The multiplier uses a modified Montgomery algorithm for point multiplication. The simulation results are obtained using...
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