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We perform a comparative analysis of metal-Si and metal-insulator-Si (MIS) contacts and quantify the impact of the contact/via resistances on logic performance. Our results show that silicide contacts account for 32% degradation in the ON current of an nFinFET (ION) compared to ideal contact. MIS contacts which lead to lowering of Schottky barrier height provide 12% performance gain at iso-energy...
We report a low specific contact resistivity of 5.5 x 10-7 Ωcm2 in nickel germanide (NiGe) contacts on n+ Ge. Data fitting with the contact resistivity model by A.M. Roy et al. (2010) suggests SBH of ~0.44eV for NiGe and ~0.55eV for Al/Ti contacts. We correlate this SBH and specific contact resistivity reduction with the dopant segregation at the NiGe/Ge interface and confirm it by SIMS analysis.
This paper reports a new contact technology comprising antimony (Sb) co-implantation and segregation to reduce Schottky barrier height (SBH) and parasitic series resistance for N-FinFETs. Experiments with shallow Sb, Ge and As co-implantation in the source/drain (S/D) regions of SOI FinFET found that all three implant species significantly reduced extrinsic resistance. The Sb implant with a 5e13 cm...
The effect of Be segregation on the Schottky barrier heights (SBH) of NiSi/Si is studied. Many elements have been shown to modulate the SBH of NiSi. However, group II elements have, to our knowledge, not been investigated before. Be is a double acceptor in Si, making it interesting for SBH modulation towards the valence band. The results show that Be implantation did not change the silicidation process...
We demonstrate for the first time contact resistance reduction using dielectric dipole mitigated Schottky barrier height (SBH) tuning on a FinFET source/drain. Different techniques for forming a SiO2/AlOx dipole layer are investigated using diodes. FinFETs, with contacts containing a SBH tuning dipole layer, are also presented. Reduction of the SBH by 100meV from the AlOx/SiO2 dipole results in a...
An overview of metallic source/drain (MSD) contacts in nanoscaled MOSFET technology is provided in this paper. MSD contacts offer several benefits for nanoscaled CMOS, i.e., extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. In order to achieve high performance MSD MOSFETs, many design parameters such as Schottky barrier...
A new type of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with self-aligned metal electrodes (SAME) is systematically characterized. New device features different from conventional poly-Si TFTs are found, and are attributed to the presence of Schottky barriers at the channel ends.
Au/IrO2/Si heterostructures were built. Their DC current versus temperature characteristics were experimentally obtained to get the corresponding Richardson plots. From these plots, the Richardson constant was estimated for these devices. Then, from the current-voltage plots at room temperature the series resistance, ideality factor and barrier height were obtained by applying the method proposed...
We present an approach to scale Rext while maintaining control of short channel effects in scaled finFETs. For FETs with fins <;20nm, an enhancement of 19% in drain current was achieved in nFETs by incorporating Al at silicide-Si interface. This Al implantation while reducing the schottky barrier height for n-Si contact by 0.4 eV, does not degrade the integrity of the junction extensions or gate...
In this article, we investigated the fabrication and characteristics of Pd germanide Schottky contacts on n-type Ge substrate. It is shown that the lowest sheet resistance and uniform Pd germanide can be obtained by a one step RTP at 400°C for 30 sec. The proposed Pd germanide/nGe contact exhibited electron Schottky barrier height and work function of 0.565~0.577 eV and 4.695~4.702 eV, respectively...
This work reports on gate voltage dependent source and drain series resistance and associated barrier height in modified double gate Schottky MOSFETs with dopant segregation. We show that in our devices the series resistances is significantly reduced by lowering the Schottky barrier height (SBH). The series resistance and the barrier have been extracted using an external series resistance method and...
Physics and technology of dopant-segregated Schottky (DSS) MOSFETs are reported. A novel approach to achieve low Schottky barrier height (phib) is proposed and demonstrated. The segregated dopants at the metal/semiconductor interface effectively modulate phib. The DSS junction significantly improves the current drivability of metal-source/drain transistors. We, for the first time, demonstrated CMOS...
We have developed a novel dual phase-modulated Ni silicide for Schottky barrier and series resistance reduction in dopant-segregated source/drain (DSS) n-MOSFETs. Using pre-silicide N2+ implant (thereafter N-implant), it is possible to selectively form interfacial epitaxial Si-rich NiSi2, reducing electron Schottky barrier(SB) from 0.7 eV to 0.34 eV while maintaining a low resistive bulk NiSi, at...
Polish Government Program ldquoNew technologies based on silicon carbide and their applications in high frequency, high power and high temperature electronics rdquo covers an project package that consists of three general tasks. The contribution presents the overview of projects in the field dealing with the design and manufacturing of power SiC semiconductor devices.
Ultra Thin Body Si-On-ONO (UTB SOONO) transistors with ultra thin spacer are successfully demonstrated and evaluated. They have shown increased driving current more than 30% compared with conventional UTB SOONO transistors with thick spacer due to reduced source/drain resistance without short channel effect degradation by using thin spacer. In this paper, it is shown that thin spacer technology is...
We report a novel contact technology comprising Selenium (Se) co-implantation and segregation to reduce Schottky barrier height PhiBn and contact resistance for n-FETs. Introducing Se at the silicide-semiconductor interface pins the Fermi level near the conduction band, and achieves a record low PhiBn of 0.1 eV on Si:C S/D stressors. Comparable sheet resistance and junction leakage are observed with...
We have developed a novel and cost-efficient silicide integration solution to achieve a hole barrier height of 215 meV and electron barrier height of 665 meV simultaneously with a single metallic silicide based on aluminum inter-diffusion. It is proposed that aluminum diffuses into PtSi and forms an alloy, which lowers the electron barrier height of PtSi due to a change in the intrinsic PtSi workfunction...
We have successfully demonstrated top-gate a-Si TFT with self-aligned nickel silicide source/drsain (S/D). We have shown, by examining contact resistance, the dominant electron injection mechanism is tunneling from silicide S/D to the channel. Further, we show that the contact resistance has no influence on device threshold and little effect on effective mobility down to L=5 mum.
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