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This paper presents design of a new stable 14T full power efficient adder circuit. The proposed circuit is designed based on Pass Transistor Logic (PTL) network using NMOS transistor only. The proposed circuit is simulated at layout level using Microwind EDA tools for 45nm technology in terms of power and voltage level at the sum and carry nodes. The proposed circuit performance is compared with a...
LTE-M, which is an abbreviated version of LTE-MTC(Machine Type Communication) can be said to have a variety of applications, including a large number of heterogeneous interconnection of large-scale network equipment. One of the most prominent problems is that the machines may have a large amount of access requests in a short time, which can easily lead to network congestion. At present, the contention-based...
Approximate or inexact computing has recently attracted considerable attention due to its potential advantages with respect to high performance and low power consumption. This paper presents the design of an approximate multiplier; this approximate multiplier consists of an approximate Booth encoder, an approximate 4-2 compressor and an approximate tree structure. The approximate design is implemented...
This paper presents architecture for a fused floating point three term adder unit. The fused or merge technique is described in this paper because in a fused technique three term addition is done in single unit. The purpose of doing this is to reduce delay, area as compared to traditional addition method. Several optimization techniques are used to reduce delay. The proposed design is implemented...
Analog Comparator is designed to compare two analog inputs and outputs a logical signal indicating which of the inputs is greater or lesser. Comparators, being an essential building block of most high speed devices like Analogue to Digital Converters, are one of the most important components used in signal processing and communication systems. Also it plays a challenging role in high speed mixed signal...
The Adder is the important part in any processor/controller design. Till date there are a plenty of 1-bit full-adder circuits which have been proposed and designed. In this paper we have a analytic and comparative description of various full adder circuits, considering various constraints like power consumption, speed of operation and area. The circuits are designed in the virtuoso platform, using...
Embedded systems have become very important in our life; they pervade all fields in today's advanced technology. With the increasing importance of these systems, designers need to estimate the performance metrics such as Delay which includes processing and communication and Power consumption. This procedure is very critical and even crucial at an early stage of design and implementation. Using GPUs...
To mitigate the total power consumption in any circuit, ASICs or FPGAs, various conventional power gating techniques has been adopted depending upon the need of the application, dynamically controlled power gating procedure is one such power gating technique which can be used to reduce the total leakage power consumption of the circuit during the runtime. It can be applied on the real time application...
In this paper we are going to study Array multiplier, Wallace multiplier, Bypassing multiplier, Modified Booth multiplier, Vedic multiplier and Booth recorded Wallace tree multiplier which have been proposed by different researchers. When the study of the various multipliers have been performed, Array multiplier is found to have the largest delay and large power consumption while Booth encoded Wallace...
In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10−18 J and its power consumption is 2.01μW. The proposed full adder is also...
Dynamic logic style is mainly used for high fan in and high performance circuits because of its smaller area and fast superior speed. This style comes with a problem of low noise margin which makes it more susceptible to noise than static CMOS circuits. It also faces some charge sharing and leakage problems. A small amount of noise at the input can cause an undesirable change at the output. Domino...
The energy efficiency and power consumption are the two primary and major concerns in present emerging applications like miniaturized bio medical sensors, pace makers, multimedia processors, etc. The energy and power consumption may decreases by multiple ways. The multiple power supply voltage design is an efficient and dominant technique for the reduction of energy and power consumption at processor...
In this paper, we propose a cross-layer design model for multiple input and multiple output (MIMO) cellular systems, to solve the problem of energy efficient communications with delay demand. We first investigate the energy efficient multiple quadrature amplitude modulation (MQAM) constellation size for each transmission stream. With the demand of the packet delay, then we propose an adaptive MIMO/SIMO...
The power consumption is a major concern for emerging applications like mobile phones, digital cameras, pace makers and multimedia processors. The power consumption can decreases by number of ways. The multiple supply voltage design is a dominant technique for the reduction of power consumption in System on Chips/Cores. The System on Chips /Cores uses level shifters and the level shifter will become...
3D technology facilitates reduction in wirelength by vertically stacking dies. Through-silicon-vias (TSVs) are used to connect inter-die signals, and the RC value of a single TSV depends on TSV dimensions, technology and used materials. The impact of TSVs on the delay also depends on the interaction between neighboring TSVs, on the length of wires connected to TSVs, and physical parameters of metal...
Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert...
The driving forces behind the need for the development of different SRAM designs are power dissipation and delay reduction along with improvement of cell stability. SRAM cell stability assessment is traditionally based on static criteria of data stability calculated through Static Noise Margin. This paper focuses on comparison of two SRAM designs by calculation of power consumption; write delay and...
This paper proposes a Low-Power, Energy Efficient 4bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power Gating Technique. Moreover, the concept of DVT (Dual-vth) scheme has been introduced while designing the full adder blocks to reduce the Leakage Power, as well as, to maintain the overall performance of the entire circuit...
One of key attributes of WBAN is to extend the network lifetime, which can be achieved by adjusting the wakeup and sleep modes of the sensor nodes. Traditional low-power methods such as channel polling and periodic duty cycling are unable to satisfy WBANs requirements due to idle listening, collision, and control packet overhead problems. In this paper, we propose an RFID-enabled MAC protocol (RMAC)...
Certain Wireless Sensor Network (WSN) applications such as patient monitoring, smart grid, and equipment condition monitoring require accurate estimation of specific WSN parameters such as end-to-end delay, reliability and power consumption. The estimation of these parameters calls for an accurate and lightweight WSN model that is suitable for the low processing capabilities of sensor nodes. In this...
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