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In this work a comprehensive SPICE model is demonstrated for perimeter-gated single photon avalanche diodes (PGSPAD) fabricated in commercial 0.5 µm CMOS process. This model simulates the trigger of an avalanche event of PGSPAD due to photon absorption, along with the quenching behavior. It also simulates the I–V characteristic, where the breakdown voltage can be modulated with applied gate voltage...
Based on systematic measurements in CMOS 40nm bulk technology, we propose a new model for isolated Extended-Drain MOS (EDMOS) transistor. Our custom Spice macro-model includes main specific effects in high-voltage devices. In particular, the model accounts for the various parasitic bipolar components (PBCs) that are fully characterized. This model can cover various architectures, from bulk-Si to FDSOI.
Silicon-controlled rectifier (SCR) has been reported with the good electrostatic discharge (ESD) robustness under the lower parasitic capacitance among ESD devices in CMOS technology. To correctly predict the performances of SCR-based ESD-protected RF circuit, it is essential for RF circuit design with accurate model of SCR device. The small-signal model of SCR in RF frequency band is proposed in...
For a high-speed and high-resolution current-steering D/A Converter (DAC), Spurious-Free dynamic range (SFDR) becomes a major limiting factor for its performance. This paper gives an overall analysis of its dynamic error due to non-ideal switching behavior and identifies the link between the 3rd or higher order harmonic distortion and digital encoding scheme for the first time so far as our knowledge...
A rapid CAD technique is presented for accurately modeling oval (stadium) shaped inductors with various shielding schemes, which features rapid simulation speed (in the range of few seconds per spiral) and significantly enhanced capacity compared to conventional electromagnetic simulation tools. Inaccuracies inherent in popular measurement and de-embedding methods are discussed and effectively factored...
A new approach to parameter extraction for on-chip symmetric transformers based on measured four-port S-parameters is proposed. Based on circuit analysis, open-loaded and short-loaded Y parameters are first used to derive the coupling parameters and all the other model parameters are derived from the corresponding analytical equations. As verified by a set of transformers fabricated on a standard...
This paper presents millimeter-wave CMOS building blocks for a high date rate wireless transceiver. The results include measured data for a 40-50 GHz broad-band low noise amplifier, a 40 GHz tuned power amplifier, and an 18 GHz voltage controlled oscillator. Also, simulation results for a 22 GHz multi-modulus prescaler is presented for implementing phase locked loop. The circuits were fabricated 0...
Design parameters, including transistor width and number of stacked stages, contribute to the efficiency of RF scavenging systems. This leads to a large design space and, as a result, designing optimal RF scavenging circuits for a given performance requirement is a difficult problem. This work presents an analytical model based on the physical design parameters of the power matched Villard voltage...
As the dimension of semiconductor device shrunk into nanoscale, characteristic fluctuation is more pronounced, and become crucial for circuit design. Diverse approaches have been reported to investigate and suppress the random-dopant-induced fluctuations in devices. However, attention is seldom drawn to the existence of high-frequency characteristic fluctuations of active device. In this paper, intrinsic...
Carbon nanotube transistor (CNT) is promising to be the technology of choice for nanoscale integration. In this work, we develop the first compact model of CNT, with the objective to explore the optimal process and design space for robust low-power applications. Based on the concept of the surface potential, the new model accurately predicts the characteristics of a CNT device under various process...
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