The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As we move to smaller CMOS technologies, the need for better testing techniques arises. We investigate the effectiveness of four testing techniques against resistive-open defects. The tests are applied to two adder topologies, namely the quasi-clocked adder and the bridge-style adder. The tests are done under full process variations for technologies down to 16nm. The test techniques based on dynamic...
In this paper, we investigate the effectiveness of different testing techniques in detecting resistive-open defects for adder circuits implemented using current and future CMOS technologies down to 22nm. We take into consideration the wide process variations associated with such technologies. The first method is based on monitoring various characteristics of the transient power supply and ground currents...
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
The use of multiple voltages for different cores is becoming a widely accepted technique for efficient power management. Level shifters are used as interfaces between voltage domains. Through extensive transistor level simulations of resistive open, bridging and resistive short faults, we have classified the testing of level shifters into PASSIVE and ACTIVE modes. We examine if high test coverage...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.