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The paper presents the FPGA implementation of the line coding scheme Non Return to Zero (NRZ). The NRZ line encoder and decoder are implemented in Verilog using MentorGraphics ModelSim Edition 10.4a. The three encoding schemes namely NRZ-Level, NRZ-Mark and NRZ-Space are implemented. The algorithms for the encoder and decoder are functionally verified and are made synthesizable using Xilinx V.10....
This paper discusses development of FPGA-based verification platform which consists of System' Verilog assertion (SVA) checker generator to synthesize SVA into Verilog code. We derive a lookup table that consists of SVA operators and their corresponding synthesizable RTL coding. Assertion checker produces single bit-1 which indicates an assertion fails while assertion collection modules must be simple...
In this paper, we present a high performance and low power hardware architecture for real-time implementation of Context Adaptive Variable Length Coding (CAVLC) algorithm used in H.264 / MPEG4 Part 10 video coding standard. This hardware is designed to be used as part of a complete low power H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL...
The recently developed High Efficiency Video Coding (HEVC) international video compression standard uses adaptive deblocking filter for reducing blocking artifacts. Deblocking filters increase both subjective and objective quality. But, they have high computational complexity. Therefore, in this paper, the first HEVC deblocking filter hardware in the literature is proposed. Two parallel datapaths...
According the universal serial cyclic redundancy check (CRC) technology, one of the new CRC algorithm based on matrix is refered, which descibe an new parallel CRC coding circuit structure with r matrix transformation and pipeline technology. According to the method of parallel CRC coding in high-speed data transmiting, it requires a lot of artificial calculation. Due to the large amount of calculation,...
PLCs have been the first choice for automation engineers for fast, reliable and robust implementation of their control algorithms for many years. Recently, with the introduction of advanced MEMS sensors and actuators and the penetration of new technologies in many diverse everyday tasks, with complicated control mechanisms and advanced calculations, it has been made clear that traditional PLCs need...
Multiplier, being a very vital part in the design of microprocessor, graphical systems, multimedia systems, DSP system etc. It is very important to have an efficient design in terms of performance, area, speed of the multiplier, and for the same Booth's multiplication algorithm provides a very fundamental platform for all the new advances made for high end multipliers meant for faster multiplication...
Hardware Description Languages and FPGAs make it possible for students to design large, complex circuits. However, HDL-based design is fraught with pitfalls that students often find difficult to understand and avoid. This paper describes a set of design guidelines for HDL-based design taken from a variety of sources and distilled into a concise list. These guidelines are intended to help students...
Airborne Electronic Hardware (AEH) development relies deeply on the quality of tools that helps the hardware artifact implementation from requirement to entity. Electronic Data Automation (EDA) tools are made to test the logic, synthesize the circuits, place and route the electronic elements and their connections prior to final implementation. A critical issue for EDA tools is its adequate safety...
Cognitive radio (CR) is a new wireless communication method that can sense local spare spectra. Then it communicates with each other using sensed available spare spectra. In a CR network, a medium access control (MAC) layer configuration determines a common set of channels to facilitate communication among participating nodes. Because spare spectra change dynamically according to time and locations,...
This paper presents the design and implementation of a forty-order FIR filter for IF GPS signal simulator with three algorithms: multiply and accumulate (MAC), add-and-shift scheme with CSD encoding (CSD), new common sub-expression elimination (CSE). Each scheme is analyzed in detail including design and optimization process to find the best one with the least hardware resource and power consumption...
This paper is on hardware prototyping of a multi-source multicast network based on random linear network coding (RLNC). There are three kinds of nodes that perform encoding, forwarding, and decoding, respectively. Each node is implemented over a NetFPGA card inside a PC. The prototype provides a realistic test bed for evaluating the hardware/time complexities of network coding applications.
Nowadays functional verification of large system-on-chip has taken about 70% to 80% of the total design effort. The large amount of IP's of current SoC's makes the work of verification engineers quite hard due to the need to guarantee that the design is bug free before it is sent to tape out. In order to reduce the time spent in the functional verification and support the verification engineers, this...
The adaptive arithmetic codec is one of the key algorithms of JPEG2000 standard. Its complexity of implementation is relatively high. In this paper Handel-C language is used as hardware description language to design the arithmetic decoder of JPEG2000. The design is debugged and synthesized under the Celoxica Design Kit. The experimental results show that we can implement arithmetic decoder to FPGA...
The paper presents a formal design methodology for reconfigurable, modular digital controller logic synthesis. The project of embedded controller starts from behavioral, graphical hierarchical and concurrent state machine description in Unified Modeling Language (UML). After the hierarchical encoding of nested and concurrent superstates, the UML state machine diagram can be directly and automatically...
This demonstration presents an integrated environment that translates a CAL-based dataflow specification [1] into a heterogeneous implementation, composed by HDL and C codes. The demonstration focuses on the capability of the co-design environment to automatically build an executable heterogeneous system implementation running on a platform composed of a processor and a FPGA from the annotation of...
Aiming at the requirements of real-time ability and good observability of result-checking in IC functional verification, a method was proposed to generate monitors automatically. Based on the requirements of the design property to be monitored, a sub-set was defined from the Property Specification Language (PSL), so that the objects to be monitored can be formally described. Based on the formal descriptions,...
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