According the universal serial cyclic redundancy check (CRC) technology, one of the new CRC algorithm based on matrix is refered, which descibe an new parallel CRC coding circuit structure with r matrix transformation and pipeline technology. According to the method of parallel CRC coding in high-speed data transmiting, it requires a lot of artificial calculation. Due to the large amount of calculation, it is easy to produce some calculation error. According to the traditional thought of the serial CRC, the algorithm of parallel CRC based on the thought of matrix transformation and iterative has been deduced and expressed. The improved algorithm by pipeline technology has been applied in other systems which require high timing requirements of problem, The desin has been inplemented through Verilog hardware description language in FPGA device, which has achieved a good validation. It has becomed a very good method for high-speed CRC coding and decoding.