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Moore's law has been the most powerful driver for the development of the microelectronic industry. This law emphasizes on lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC/Si integration, which is a very complicate...
There are many factors which will affect the final result of TSV filling, such as ratio of the additives including accelerator, suppresser, leveler and so on. Complicated environment is also hard to control exactly. If we want to form the “bottom up” in the plating, there must be comprehensively consideration of all factors. Many studies have focused on the effect of additives on the plating uniformity...
Through silicon via technology is one of the critical and enabling technologies for 3D packaging. 300 mum deep vias with a diameter of 50 mum were filled by copper electroplating with CuSO4 and H2SO4 as base electrolyte. Chloride ions, accelerator and leveler were added. The effect of leveler concentration on filling performance was studied. Electrochemical measurements were used to investigate the...
The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of copper. The impact of seed layer nature on filling ratio and void formation will be discussed with respect to via diameter and via depth. Based on the spherolyte Cu200 the electrolyte for the copper electrochemical deposition was modified for good filling behavior. Thermomechanical modeling and simulation...
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