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Neutron irradiation of a multiple bit upset sensitive bulk CMOS SRAM prior to heavy ion exposure is shown to significantly increase the number of bits upset per event observed. The displacement damage induced by the neutron exposure prior to the single event experiment is shown to have little to no impact on the performance of the SRAM. However, the neutron fluence is able to induce small changes...
In this paper, the characteristic variability in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) is experimentally studied. Variation sources in SNWTs are extracted for the first time, taking into account the strongly-confined geometry induced quantum effect, quasi-ballistic effects, as well as the parasitic quantum resistance at the interface of 1D channel and 3D wide S/D regions. The measured...
SRAM, the important memory component, has been widely used in design of digital and communication circuits. SRAM is also an effective vehicle for process development and qualification due to its complexity and high density in which an engineer is able to detect the process issues. Generally SRAM??s yield is used as an indicator of the semiconductor nodes yield. In this paper we present the analysis...
Spacer-defined fin-patterning results in double/quadruple fin density and hence is attractive for high performance 32-nm CMOS applications. For the first time 55-nm gate-length FinFET SRAMs with resist- and spacer-defined fins are electrically compared. Due to short-range process variations, SRAM bit-cells with spacer-defined fins show approximately 2.5 times higher variability in static-noise-margin...
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