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The NMOSFET-only pass gates used in some digital CMOS applications, such as the Field-Programmable Gate Arrays (FPGAs), are apparently vulnerable to Positive Bias Temperature Instability (PBTI). Here we discuss the impact of PBTI frequency and workload on high-k/metal-gate NMOSFETs in terms of Capture-and-Emission Time (CET) maps and quantitatively explain the degradation of our test circuit. From...
The impact of aging effects, in terms of circuit performance and reliability, is one of the new recent challenges in VLSI design targeting the most advanced CMOS technologies. This work proposes an effective methodology to aging analysis in flip-flops. The estimation method proposed previously for combinational logic gates is exploited and improved herein to address such sequential gates. Three different...
The dawn of manycores begun many years ago. Technology offers many ways to find a point — given by the application scenario — within the triangle performance, reliability, and power consumption. These factors mainly ascertain the effectiveness of a microarchitecture. The dusk of the manycore era is bound by the technology which will come out on top, an activity which is not always determined by pure...
Graphene nanoribbon FETs (GNRFETs) are promising devices for beyond-CMOS nanoelectronics due to their excellent carrier-transport properties and potential for large-scale processing and fabrication. This paper combines atomistic quantum-transport modeling with circuit simulation to perform technology exploration for GNRFET circuits. Results indicate that GNRFETs offer significant gains over scaled...
In this paper, we study the influence of the doping profile in the drift region on performance and reliability of RF-NLDMOS transistors in a 0.13 mum SiGe-BiCMOS technology. Two different drift region designs were investigated by simulation and experiment. We show that the design with a shallow compensation implant delivers a significantly improved HCI robustness at a similar level of RF and DC performance...
In this paper, we examine the current-voltage (IV) and capacitance-voltage (CV) characteristics of self-aligned (SA), planar block oxide (BO) metal-oxide semiconductor field-effect transistors (MOSFETs) using technology computer-aided design (TCAD) tools. For the first time, a comparison of the different types of BO MOSFETs, such as fully depleted silicon-on-insulator (FDSOI) FET with BO (bFDSOI),...
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper transistor has been employed to compensate for leakage current of pull down (NMOS) network. However, to maintain acceptable noise margin level in sub-100 nm technologies, large PMOS is necessary, which results in substantial...
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