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The scaling of the device, for the application of VLSI and ULSI technology, is necessary. For this purpose a novel model of DG MOSFET has already been designed, after that FinFET and nanowire techniques introduced. But to further improvement for the latest technologies, the CDSG MOSFET, a novel model has an advantage of the scaling. Using this CSDG MOSFET beyond 22 nm technology, the effect on the...
The semiconductor devices are scaled into nanotechnology range and facing the short channel effects and subthreshold characteristics, which restrict the application of traditional planar devices. To solve these problems, a novel device geometries as double-gate MOSFET has been designed. In this work the double-gate model has been extended to design a Cylindrical Surrounding Double-Gate MOSFET and...
In Micro and Nano Technology, the downscaling of semiconductor devices requires the usage of alternative semiconductor material for SiO2 as the gate dielectric. It requires new structure so that the higher current can be achieved. In view of this, in the present paper a structure of double-gate MOSFET with HfO2 has been analysed. This paper includes an effect of threshold voltage on symmetric double-gate...
The Double-Gate MOSFET can be used to design the nanotechnology based switches at the range of Terahertz for transceiver processes. In this research, the switching frequency with the help of transconductance for Terahertz Double-Gate MOSFET has been analyzed. The switching transient has been observed with inclusion of currents. It will be suitable for the application of nanotechnology regime.
The objective of the paper is to design a physical level chip for floating point multiplication using the concepts from Vedic Mathematics with VLSI 90nm technology. Vedic Mathematics has been a successful methodology in computing various basic calculations by faster means. But, its inefficiency to compute decimal calculations and controversy with speed, timing and power parameters in the digital chip...
Radiation induced soft errors are a serious concern not only for memories but also logic circuits. Amongst the several proposed countermeasures, Bulk Built-in Current Sensors represent a promising approach with fast response times and reasonable costs in terms of area and power. However, these circuits, as well as similar sensors that measure substrate effects, are strongly susceptible to substrate...
This paper presents the design and physical layout implementation of constant v/f method for speed control of an AC induction motor using VLSI 90nm technology. This method falls under the category of VVVF drives, that is based on Sinusoidal pulse width modulation technique (SPWM). SPWM plays an important role in the minimization of lower order harmonics and switching power losses in the power converters...
Current CMOS technologies show an increasing susceptibility to a rising amount of failure sources. This includes also radiation induced soft errors, which requires countermeasures on several design levels. Hereby, Bulk Built-In Current Sensors represent a promising approach on circuit level. However, it is expected that these circuits, like similar sensors measuring substrate effects, are strongly...
The objective of the paper is to design and analyze a physical level chip for Fast Fourier Transform using the concepts from Vedic Mathematics with VLSI 90nm technology. Vedic Mathematics in certain fields are faster than regular mathematical computations. Implementing the idea of Vedic mathematics in designing a Fast Fourier Transform chip will improve the efficiency of calculation and will produce...
The present paper explores and analyses the performance of Carbon Nano Tube Field Effect Transistor (CNTFET) technology in analog domain through its application as a basic current mirror. 32nm channel length-single walled-one tube CNTFET technology has been assessed and compared with 45nm, 32nm and 22nm NMOS technologies through HSPICE simulations of current mirror circuitry. Different methods of...
In the paper knowledge representation approaches for two engineering applications are discussed. Our focus is on the VLSI systems and MEMS design case study. Cognitive features are shown to be important components in data curation for our case study.
Carbon nanotubes (CNTs) have been proved as an emerging interconnect material for future nano and deep submicron level technologies. CNTs are more advantageous than copper or other interconnect materials because of their robustness to electromigration. In this paper, single-wall CNT (SWNT)-based interconnects are modeled and the effects of crosstalk are evaluated. On comparing the crosstalk effects...
Nanowire crossbar is an efficient nanoscale architecture which can be used for logic circuit design. In this work, we study the application of nanowire crossbar in logic circuit implementation. To evaluate the performance of crossbar architecture compared to the conventional MOSFET logic design, we have implemented logic circuits using both approaches. The equivalent circuit models of the crossbar-based...
Multi-wall carbon nanotubes (MWNTs) have potentially provided an attractive solution over single-wall carbon nanotube (SWNT) bundles at deep sub-micron level very large scale integration (VLSI) technologies. This paper presents a comprehensive analysis of propagation delay for both MWNT and SWNT bundles at different interconnect lengths (global) and shows a comparison of area for equivalent number...
For implementing nanotechnology in VLSI, the replacement of silicon dioxide (SiO2) in gate dielectric becomes a challenging issue. Our innovation is to use Zirconium Silicate (ZrSiO4) as the replacement of SiO2 in gate dielectric, while companies like AMD, IBM and Intel have announced plans to replace the gate dielectric with Hafnium Silicate (HfSiO4). The implementation of ZrSiO4 is one of several...
The following topics are dealt with: wireless sensor network; data mining; network security; nanotechnology in VLSI; sign language recognition; biometrics; Wi-Max; image registration; and vehicular technology.
In Part II of this paper, a comparison of the most representative flip-flop (FF) classes and topologies in a 65-nm CMOS technology is carried out. The comparison, which is performed on the energy-delay-area domain, exploits the strategies and methodologies for FFs analysis and design reported in Part I. In particular, the analysis accounts for the impact of leakage and layout parasitics on the optimization...
Leakage power is the main dominant source of power dissipation for Sub-100nm VLSI circuits. Various techniques were proposed to reduce the leakage power dissipation; one of these techniques is Multi-Threshold voltage. In this paper, the exact and optimal values of Threshold Voltage (Vth) for each transistor of the design are found for any sequential circuit. This is achieved by applying Artificial...
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper provides a comprehensive overview of the types and sources of all aspects of process variations in driver -interconnect-load system. The primary sources of manufacturing variation include Deposition, Chemical Mechanical Planarization (CMP), Etching, Resolution Enhancement...
The following topics are dealt with: emerging nano-circuits and systems; analog A/D converters; embedded electronics; computer arithmetic and clock circuits; biomedical and bio-inspired engineering systems; deep submicron design and automation; memory design and techniques for managing process parameter variations; RF, microwave and optical systems; amplifiers; low-power design and design automation;...
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