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Low power and reliable “Fab-friendly” resistance switching memory devices (ReRAM) are achieved by controlling composition and morphology of simple binary transition-metal oxides (MeOx) and metal-nitride electrodes (Ti-N) through physical vapor deposition (PVD) methods. Adjusting PVD deposition parameters influence crystalline structure, surface morphology, and stoichiometry, which subsequently influence...
The long retention, more than 10 years at 85degC, and excellent thermal reliability memory of TiN-CuxO-Cu (with TiN cap layer as top electrode) is reported. TiN cap layer results in more stable reset from low resistance state (LRS) to high resistance state (HRS) under positive pulse and SET under negative pulse, which is beneficial for providing large programming current or voltage on the resistive...
In this paper, the bipolar resistive switching memory using HfO2 film with a TiN/Ti bi-layer electrode is reported. A robust endurance (>106 cycles) and long data retention (>10 years at 200degC) of this memory device was achieved. The memory also shows fast operation speed (~10 ns), low operation power and capability of multi-level operation.
Test structures for the electrical characterization of ultrathin conductive (ALD) films are presented based on buried electrodes on which the ultrathin film is deposited. This work includes test structure design and fabrication, and the electrical characterization of ALD TiN films down to 4 nm. It is shown that these structures can be used successfully to characterize sub 10 nm films.
In this paper, the characteristics and mechanism of the transition metal oxide (TMO) based resistive switching memory (RRAM) devices were addressed. The results show that doping in oxide matrix materials, electrode material, and operating mode of the set/reset process may significantly affect the resistive switching behaviors of RRAM devices. Optimizing the dopants and matrix materials, electrode...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
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