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This paper discusses some specific circuit, and analog DFT techniques and methodologies used in integrated power management (PM) systems to overcome challenges of mixed-signal SoC qualification. They are mainly targeted at achieving the following: 1. Enabling the robust digital and system level test and burn-in (BI) with external supplies by disabling the on-chip PM with robust power-on performance,...
This paper presents a method for modeling chip-package resonance using impulse response and for measuring waveforms under varying conditions. We evaluated chip-package resonance with the following variations in conditions: (i) with and without on-package capacitors; (ii) differing positions on the chip; (iii) differing points of observation outside the chip (probe points for the package capacitor...
The design of integrated circuits, especially system-on-chips (SoC) is now constrained by many parameters such as speed, energy but also the robustness to process variability. Indeed, controlling the speed and the energy in a complex SoCs - which adopt the globally asynchronous locally synchronous (GALS) paradigm - require specific power supplies and clock generators as actuators and dedicated sensors...
As IC technology scales down, signal integrity issues such as power supply noise and clock skews are becoming one of the major concerns of gigahertz system-on-chip (SoC) design. Considering that one of the most important mechanisms to degrade signal integrity is electromagnetic interference (EMI), this paper analyzes the effectiveness of a clock duty-cycle (CDC) modulation technique to enhance SoC...
This paper describes the design of a system-on-a-chip (SoC) that integrates ADC, DAC, DDC and DDS blocks for communication system applications. Special considerations are given to the noise, power and ground, ESD and packaging design to ensure design success. The described chip has been manufactured and achieved first time silicon success.
In the foreseeable future, VLSI design will meet a couple of explosions: explosion of power, explosion of integrity attackers including power integrity and signal integrity and explosion of NRE (non-recurring engineering cost). A remedy for power explosion and explosion of integrity attackers lies in ldquovoltage engineeringrdquo. A remedy for the NRE explosion is to reduce the number of developments...
This paper deals with the design of power supply distribution network in CMOS System-on-Chips to reduce electromagnetic emissions. The main sources of both conducted and radiated emissions are pointed out and the most popular solutions for these problems are summarized. Based on that, the paper shows a new power supply network and grounding scheme that strongly mitigate the off-chip propagation of...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
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