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Heterogeneous computing platforms including both processors and field programmable gate arrays (FPGAs) represent an attractive solution for balancing software flexibility with high performance and energy efficiency of custom hardware modules. Furthermore, the dynamic partial reconfiguration (DPR) capabilities of modern FPGAs allow virtualizing the available area to support several hardware modules...
Increasing user demands for timely and complex analysis of large amounts of collected data in the IoT era are pushing the computing servers from the cloud to the Edge where the energy budgets are much tighter. Building a HPC for the Edge is thus a considerable challenge. In terms of processors, we are observing a trend of making traditional high-performance processors more energy-efficient. On the...
Non-volatile memory express (NVMe) based SSDs and the NUMA platform are widely adopted in servers to achieve faster storage speed and more powerful processing capability. As of now, very little research has been conducted to investigate the performance and energy efficiency of the state-of-the-art NUMA architecture integrated with NVMe SSDs, an emerging technology used to host parallel I/O threads...
Multicore communications processors have become the main computing element in Internet routers and mobile base stations due to their flexibility and high processing capability. These processors are designed and equipped with enough resources to handle peak traffic loads. But network traffic varies significantly over time and peak traffic is observed very rarely. This variation in amount of traffic...
The rate of network packets encapsulating requests from clients can significantly affect the utilization, and thus performance and sleep states of processors in servers deploying a power management policy. To improve energy efficiency, servers may adopt an aggressive power management policy that frequently transitions a processor to a low-performance or sleep state at a low utilization. However, such...
This paper presents an analysis of the efficiency of traditional fault-tolerance methods on parallel systems running on top of Linux OS. It starts by studying the occurrence of software errors at systems presenting different levels of complexity, from sequential bare metal to parallel Linux applications. Then two traditional fault-tolerance mechanisms (triple modular redundancy and duplication with...
Processor hardware performance counters have recently improved in quality and features, while performance monitoring support in Linux has been significantly revamped with the development of the perf_events subsystem, which contributed in making performance analysis an increasingly common practice among developers. However, no performance analysis is possible without an efficient monitoring interface...
PWCS (Probabilistic Write / Copy-Select) is a new kind of lock-free synchronization mechanism with wait-free characteristics proposed by Nicholas Mc Guire at the 13th real-time Linux workshop, which utilizes the inherent randomness of the modern computer systems. It aims at addressing the multi-reader - single-writer problem in Linux. Based on the original label-based PWCS, we propose a hash-based...
Single-ISA heterogeneous multicore processors have gained increasing popularity with the introduction of recent technologies such as ARM big.LITTLE. These processors offer increased energy efficiency through combining low power in-order cores with high performance out-of-order cores. Efficiently exploiting this attractive feature requires careful management so as to meet the demands of targeted applications...
Virtualization has become a key technology used in modern data centers. What began as a tool for server consolidation and energy efficiency has grown into an enabler for cloud computing. Cloud computing has become an accepted best practice for data centers. Virtualization is also becoming a key component of embedded and real-time systems in automotive systems, game consoles, and industrial settings...
TILE-Gx processors that have emerged in recent years can be considered as the representative of prevailing many-core processors. The available TILE-Gx processors are featured with directory-based cache coherence protocol, two-dimensional mesh networks and up to 72 on-chip cores. In this paper, we study and analyze problems of performance scalability and network collision of many-core processors using...
In-memory big-data processing is rapidly emerging as a promising solution for large-scale data analytics with highperformance and/or real-time requirements. In-memory bigdata workloads are often hosted on servers that consist of a few multi-core CPUs and large physical memory, exhibiting the non-uniform memory access (NUMA) characteristics. While large pages are commonly known as an effective technique...
This work deals with the problem of developing embedded multi-core systems, under time-to-prototype and high performance constraints, by exploiting reconfigurable logic. In particular, the paper focuses on the early analysis activities, performed by means of native simulation technologies, and then on the full development of an embedded multi-core platform composed of four LEON3 soft-processors and...
There is a strong relationship between scientific research and technology advancement. The former generally focuses on studying phenomena happening in the real world, the latter improves tools that are at the basis of this research. From this perspective, information and communication technologies allow the implementation of ever faster tools for analyzing data generated by experiments. The aim of...
The memory subsystem of modern multi-core architectures is becoming more and more complex with the increasing number of cores integrated in a single computer system. This complexity leads to profiling needs to let software developers understand how programs use the memory subsystem. Modern processors come with hardware profiling features to help building tools for these profiling needs. Regarding...
Live virtual machine migration is an essential tool for dynamic resource management in current data centers. Many techniques have been developed to achieve this goalwith minimum service interruption. In this paper, we proposea pre-copy live VM migration using Distributed SharedMemory (DSM) computing model. The setup is built usingtwo identical computation nodes to construct the environmentservices...
The core functionality of a network is packet processing. Fast Path is the functional area that handles processing of packets. The Fast Path functionalities is predominantly hardware driven and is very difficult to port on other platforms. This is because the APIs (Application Programming Interfaces) used for developing fast path applications is system on chip specific. To enable the easy migration...
Process schedulers are part of the core functionality of an operating system (OS), and have been enhanced over the years to account for multiple cores in the processors and to support multi-threaded applications. In this study, we investigate the impact of the Linux scheduler's load-balancing algorithm on the performance of multi-threaded OpenSIPS (an open source SIP proxy server, SPS) running on...
Modern FPGA-based Multiprocessor Systems-on-Chip (MPSoCs) support dynamic reconfiguration of processing elements (PEs) such as processors and accelerators. The reconfiguration improves the flexibility of the system due to the dynamic and partial exchange of PEs. However, the design of reconfigurable MPSoCs leads also to higher complexity in programming due to the huge design space. To bridge this...
Hardware Trends. Moore's law paved the way for doubling the transistors in the same chip area with every generation. However, with the end of Dennard's scaling, voltage and hence the power draw of transistors is no longer dropping proportionally to size. As a result, modern processors cannot use all parts of the processor simultaneously without exceeding the power limit. This manifests as an increasing...
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