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A method for fabrication of tri-gate polycrystalline silicon (poly-Si) transistors with short channel length and width is proposed and demonstrated without employing costly lithographic tools. Specifically, the method employs a spacer formation technique to extend source and drain regions so as to scale down the channel length below sub-lithographic dimension. Concurrently, the channel width is scaled...
The world's most downsized ferroelectric-gate field effect transistors (FeFETs) with good electrical properties were successfully fabricated, which were developed as memory cells of ferroelectric-NAND (Fe-NAND), the next generation NAND flash memory. 0.54 μm- and 0.26 μm-gate FeFETs were fabricated and characterized. The stacked gate structure of the FeFETs was Pt/SrBi2Ta2O9(SBT)/Hf-Al-O/Si. Cross-sectional...
Here we report on top-contact organic TFTs and complementary circuits fabricated using stencil masks with a resolution of 1 μm. The stencil masks were manufactured on silicon-on-insulator (SOI) wafers, with the buried SiO2 serving as an etch stop during the formation and patterning of the Si membrane, which has a thickness of 20 μm [10,11]. Openings in the Si membrane were created by electron-beam...
AlGaN/GaN heterostructure field effect transistors with different gate recess depths have been fabricated using an ICP etch process. Subsequently, electrical DC characterization has been performed. The results have been compared with the theoretical predictions according to the simple charge control model, showing that for a given AlGaN/GaN structure there is an optimum thickness with respect to the...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
The integration of vertical natural capacitors (VNCap) into existing backend-of-line (BEOL) stacks is an important aspect to enable radio-frequency and mixed signal features without extra mask costs. From manufacturing and reliability point of view these devices can be rather challenging since they may contain millions of vias and meters of metal interconnects. In this paper we will discuss the robustness...
We present the conductance properties of resonant tunneling heterostructures, laterally confined by a Schottky gate so that the confinement can be varied in a continuous and controlled way. Data on dots with nominal diameters in the submicron range are reported.
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