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A method for fabrication of VeSFETs, three-dimensional fin-type MOS transistors is presented. The VeSTIC process was developed and experimentally implemented in ITE. The test devics were manufactured, and their electrical characteristics were measured. Methods for extraction of a set of the VeSFET physical parameters are proposed based on the device compact model. The flat-band voltage, mobility and...
Practical manufacturing technique to reduce characteristic variation of 40 nm CMOS device has been developed. Novel feed-forward (FF) system at gate formation for tight gate length control, and FF techniques at both halo implantation and Spike RTA for device centering have been applied. In addition, adjusting wafer notch angle at each critical process step has been utilized to suppress within-wafer...
TaN was widely used as Cu diffusion barrier in CMOS Cu-BEOL technology, in which it was removed by CMP process. Some work was done on TaN etch by Br/Cl-based gas for metal gate application. But seldom work was done for TaN etch in CF-based gas. In this work TaN etching in CF4/CHF3 gas was investigated on CVD alpha-Si substrate for CMOS compatible MEMS/Sensor application. To avoid resist poisoning...
Foreseen operation at sub-THz frequencies of Schottky contacts for diodes and transistor gates on GaAs based heterostructures requires area reduction down to 0.1×1 microns, and wet chemical processes. We report on the compatibility of Trilayer Electron-beam Lithography with such wet processes.
This paper presents a unique gate structure for reducing shorts between word lines on charge-trapping flash cell memory. In the early stage of developing sub-45 nm half-pitch word line by a self-aligned double patterning (SADP) technology, the cell array suffered from abnormal intrinsic word line-to-word line shorts, ca. 96.3% of the bridge rate on the 72 Mb cell memory, due to the formation of polysilicon...
In this paper, we demonstrate a self-aligned gate-first process for fabrication of T-gates without much degradation of fτ. The device layer structure is shown. The fabrication process involves formation of W/Cr gates using a self-aligned gate-etch process similar to the InGaAs MOSFET technology reported by Rodwell et. al. [2008, 2009]. After formation of a 130 nm long gates, graded InGaN/InN-based...
This paper reports the successful fabrication of a field emitter array with a built-in multi-electrode lens, such as a quad-gate and a penta-gate FEA. The fabrication is based on an etch-back technique.
In this paper we report for the first time, a method of generating wide gate recess structure in single recess step by the help of a bi-layer lithography technique, which can be used to generate varying gate recess width by varying developmental time. It is established that the gate recess structure decides the Schottky breakdown voltages in these devices. The distance from gate edge-to-n+ in the...
In the emerging field of large area electronics polymer foil substrates play a key role in large area and flexible electronic, illumination and display systems. Compared to silicon, however, coatings on polymer substrates and in particular foils are challenging to pattern on a scale below 10 mum due to surface roughness and surface defects caused by industrial manufacturing processes. The presentation...
We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum2 6T-SRAMs, with W-filled contacts. Alignment to other 193 nm immersion litho levels shows very good overlay values les20 nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
The patterning the contact holes by photolithography process, in this case polysilicon contacts, is the process to produce electrical connection between metal layer and polysilicon gates or metal layer and source/drain. The photolithography process can control size and shape of the contact hole patterns on photoresist before permanently patterned by etching process and then metallization. The contact...
Emission spectroscopy of plasma-excited chemical species is widely used for generalized chemical analyses in bench-top systems. This paper explores the use of pulsed microdischarges between two and three electrode microstructures, which operate in air at atmospheric pressure, for use in handheld chemical analyzers. Pulsed microdischarges are fired between two-electrodes spaced apart by 0.2-2 mm. Synchronized...
This paper presents a shallow trench isolation technique using plasma etching, LPCVD oxide fill, and planarization. This novel planarization technique applying X-ray lithography and isotropic O2-plasma etch needs no additional mask for block resist patterning over large isolation areas. MOSFETs have been fabricated showing nearly zero channel width loss and no threshold voltage shift down to 0.8 ??m...
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