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In addition to global stained epitaxial SiGe layer, silicon nitride as contact etching stop layer (CESL) is to be deposited on the whole device to enhance the straining effects. As found in this paper, 10μm/10μm (channel length/ width) PMOS devices at various temperatures with or without stain are referred. To focus on the SiGe alone, the 1.5nm silicon cap following epi-taxial SiGe is to be considered...
The use of nanoprobing techniques to accomplish transistor parametric data extraction has been widely reported as a method of failure analysis in nanometer scale science and technology. Certain failure mechanisms causing parametric transistor fails are, however, not always successfully identified, even using advanced imaging tools, such as transmission electron microscopy (TEM). Therefore, additional...
The gate critical dimension (CD) variation of ultra-large-scale integrated circuit (ULSI) devices should be reduced to improve the production yield. An examination of the formulation of a gate-CD model for the transistor area, including the static random access memory (SRAM), was conducted taking the topographical and layout effects into account. It was found that the formulation of a gate CD for...
The logic gate threshold voltage controllable single metal gate FinFET CMOS inverter constructed by the 3T-PMOS and 4T-NMOS have successfully been fabricated. The accurate current matching and the logic gate threshold voltage tuning by Vg2 in the 4T-NMOS have been demonstrated. A higher WF metal would be more suitable for the proposed FinFET CMOS.
We report a CMOS-compatible vertical MOSFET, which incorporates a frame gate architecture suitable for application in RF circuits. Fabricated surround gate vertical MOSFETs with the frame gate architecture show no degradation of short channel effects when the channel length is scaled, while control devices show significantly degraded sub-threshold slope and DIBL. The frame gate vertical MOSFETs show...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
We have observed new charge trapping phenomena in sub-80-nm DRAM recessed- channel-array-transistor (RCAT) after Fowler-Nordheim (FN) stress. Gate stack process strongly affected the charge trapping and the trap generating in oxide bulk and interface of RCAT. According to the trapped charges and/or the generated traps after FN stress, the data retention time and writing capabilities of DRAM were dramatically...
Fabrication of self-aligned silicide of CoSi2 on source/drain areas in a tungsten polycide (WSix/poly) process is demonstrated. CoSi2 is formed by RTA under conditions identical to the poly gate process, i.e. no extra capping layer is required on top of the WSix gate. The materials interactions of WSix with Co films during RTA and subsequent wet etching steps have been studied. Transistor results...
This paper presents a shallow trench isolation technique using plasma etching, LPCVD oxide fill, and planarization. This novel planarization technique applying X-ray lithography and isotropic O2-plasma etch needs no additional mask for block resist patterning over large isolation areas. MOSFETs have been fabricated showing nearly zero channel width loss and no threshold voltage shift down to 0.8 ??m...
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