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Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating...
This paper presents a new method to automatically generate hierarchical placement rules, which are crucial for a successful analog placement. The method is based on a novel symmetry computation method, introducing the structural signal flow graph. Five types of proximity, matching and symmetry constraints are determined. According to the priority of the constraint types, a constraint requirement graph...
In this paper a very low voltage low power CMOS Low Noise Amplifier (LNA) suitable for ultra low power applications is presented. A new design methodology for noise and power consumption optimization is described. By using forward body bias (FBB), the proposed LNA, implemented in a 0.13μm CMOS process, can operate at 0.5V supply voltage, at 2.4GHz. Post layout simulation results show that it achieves...
This paper describes the design of an 8-bit fully differential pipelined analog-to-digital converter (ADC). The design methodology employed in this work follows a technique of allocating appropriate error budgets to the various ADC errors such that the maximum differential nonlinearity (DNL) error is less than 0.5 least significant bits (LSB). Simulation results show that the ADC maximum DNL errors...
Advanced layout parameters in the deep sub micron technologies impact the integrated circuit original design performance and change the schematics target specifications. Physical parameters such as stress effects and well proximity effects are more affecting analog and mixed signal designs in nanometer IC technologies. This paper presents a physical aware design methodology that enables analog and...
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