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Short-gate length epitaxial multi-(core/shell) p-type nanowire (NW) transistors with high-permittivity dielectric and metal gate were fabricated and their electrical properties examined. Silicon NWs were first of all patterned in ultrathin silicon-on-insulator wafers by lithography and etching. Selective epitaxial growth of ...
In this study, the process technology of contact-etching stop-layer (CESL) with LPCVD or PECVD is performed by interlayer-dielectric-SiNx stressing layer to form the tensile or compressive strained n/p MOSFETs. Because the strain effect on MOSFET devices is finite, the promoting performance of source/drain current is increased more while the channel lengths of the devices are decreased more. This...
The uni-axial compressive strain from e-SiGe S/D combined with dynamic body biases effect on flicker noise of pMOSFETs is presented in this paper. This compressive strain contributes higher mobility but the worse flicker noise in terms of higher SID/ID2 becomes a potential killer to RF/analog circuits. Forward body biases (FBB) can reduce the flicker noise but the degraded body bias effect in strained...
In this paper, the hot-carrier induced oxide trap and its correlation with enhanced degradation in strained CMOS devices have been reported for the first time. First, the ID-RTN (drain current random telegraph noise) has been employed to study the HC stress induced slow oxide traps in strained nMOSFETs and pMOSFETs. Secondly, different behavior of the slow traps in nMOSFET and pMOSFET has been observed...
An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS "stressors"). A stress memorization process and a tensile-stressed liner film are used to induce tensile strain in the NMOS (NMOS "stressors"). With optimization, the different...
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