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In this paper, we explore the pessimistic voltage guardbands of two multicore x86-64 microprocessor chips that belong to different microarchitectures (one ultra-low power and one high-performance microprocessor), when programs are executed on individual cores of the CPU chips. We also examine the energy and temperature gains as positive effects of lowering the voltage in both chips while preserving...
Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes...
This paper describes the design, microarchitecture, and performance of the latest Fujitsu SPARC64 XII 12 core microprocessor which has been developed for high performance, mission critical servers. Dual instruction pipelines, 8-way SMT (Simultaneous Multi-Threading), a high CPU frequency of over 4 GHz, and a 12 core design have doubled the chip performance compared with the previous SPARC64 X+, while...
The following topics are dealt with: neurosynaptic integrated circuit; digital microfluidic biochips; supercomputer; flip-flops; ARM-FPGA; CPU; system-on-chips; vehicle intelligence; convolutional neural networks; silicon-on-insulator; STT-RAM; video signal processing; and CMOS integrated circuit.
Multipliers are the most important block in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the increasing constraints on delay, design of faster multipliers is emphasized. Among several multipliers, Vedic multipliers are preferred for their speed of operation. Among the sixteen sutras in Vedic multiplication techniques our proposed “URDHVA TIRYAKBHYAM” a most efficient...
In this paper, we explore the trade-offs between sensors' and models' accuracy for state estimation in battery management systems. If, in a battery pack, high quality sensors were used, then state estimation (or monitoring) would be improved at the expenses of hardware costs. On the other hand, if accurate models were used within the estimation algorithms, better estimates could be produced at the...
Optical interconnection is a potential substitute for electrical interconnection in the chip integration field, as it can ultimately solve the problems such as crosstalk and electric migration brought by electrical wires. In the paper, a short frame asynchronous optical communication protocol is proposed to implement the inter-chip optical communication between the microprocessor and the static memory...
This article consists of a collection of slides from the author's conference presentation on IBM's zNext, a 3rd generation high frequency microprocessor chip. Some of the specific topics discussed include: an overview of the product design and system specifications; speed and processing capabilities; improvements to feed processing; system architecture design; applications for using zNext; and future...
Defect density and variabilities in values of parameters continue to grow with each new generation of nano-scale fabrication technology. In SRAMs, variabilities reduce yield and necessitate extensive interventions, such as the use of increasing numbers of spares to achieve acceptable yield. For most microprocessor chips, the number of SRAM bits is expected to grow 2× for every generation. Consequently,...
We present the design and implementation details of a time-division demultiplexing/multiplexing based scan architecture using serializer/deserializer. This is one of the key DFT features implemented on NVIDIA's Fermi family GPU (Graphic Processing Unit) chips. We provide a comprehensive description on the architecture and specifications. We also depict a compact serializer/deserializer module design,...
In this paper, we present a software approach for localization of faulty components in a 2D-mesh Network-on-Chip, targeting fault tolerance in a shared memory MP2SoC architecture. We use a pre-existing and distributed hardware infrastructure supporting self-test and de-activation of the faulty components (routers and communication channels), that are transformed into “black hole”. We detail the software...
Internet of Things is a key component of next generation information technology. And the key of Internet of Things is RFID. Now Internet of Things brings new requirements to handheld UHF RFID reader. This paper proposed a complete solution of handheld UHF RFID reader based on AS3991 and AM3517 for The Internet of Things. This reader uses AS3991 UHF RFID reader chip , which conforms to ISO18000-6C...
In this paper, we propose an automated technique to identify the reasons for un-testable faults and, an interactive Low Coverage Analysis flow to expedite the coverage analysis step, in scan ATPG. We seamlessly use an implication graph to keep track of the reasons that are responsible for each conflict encountered during ATPG. As ATPG progresses, for each fault, all the reasons arising from ATPG constraints...
Demand is increasing daily for a robust VLSI chip that is useful for operating under a radiation-rich space environment, such as spacecraft, space satellites, and space stations. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory...
State-of-the-art multi-core reconfigurable processors do not exploit the full potential of simultaneous multi-tasking with run-time adaptive reconfigurable fabric allocation. We propose a novel run-time system for simultaneous multi-tasking in a multi-core reconfigurable processor that adaptively allocates the mixed-grained reconfigurable fabric resource at run time among different tasks considering...
Base on Intel Math Kernel Library (MKL), the paper mainly focus on the research and realization of software radar signal processing, which includes magnitude, accumulation and Constant-False-Alarm-Rate(CFAR). Firstly, paper introduces simple signal processing flow of conventional search radar based on ship, then gives the detailed analysis on magnitude, accumulation and CFAR processing module's computing...
Stencil computation is one of the important kernels in scientific computations, however, the sustained performance is limited by memory bandwidth especially on multi-core microprocessors and GPGPUs due to its small operationalintensity. In this paper, we propose a scalable streaming-array (SSA) of simple soft-processors for high-performance stencil computation on multiple FPGAs. The SSA architecture...
The IBM zEnterprise z196 processor chip is an energy efficient high-frequency, high-performance design that implements 4 processor cores optimized for maximum single-thread performance. Chip energy efficiency is improved by 25% compared to the previous 65nm design, which enables the processor chip to run at product frequency of 5.2 GHz, providing a significant performance boost for the z196 system...
Supply voltage (VCC) scaling is the most effective technique for reducing the energy consumption of microprocessors. Since VCC scaling increases the impact of parameter variations on circuit performance and functionality, circuits eventually fall out of specification, thus limiting the minimum operating supply voltage (VCCMIN) for the microprocessor. The last-level cache (LLC) often determines VCCMIN...
The boom of multicore microprocessors seen in recent years has made it so any personal computer (PC) can be used as a small parallel computer. In this new environment a review of the algorithms and the tools used for the analysis of electrical systems is needed in order to take advantage of all the computing power available today on a PC. This paper presents the parallelization of an optimal power...
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