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Customized application-specific processors called ASIPs are becoming commonplace in contemporary embedded system designs. Neural networks are an interesting application for which an ASIP can be tailored to increase performance, lower power consumption and/or increase throughput. Here, both the bidirectional associative memory and hopfield auto-associative memory networks are run through an automated...
The fast and accurate processor simulator is an essential tool for effective design of modern high-performance application-specific instruction set processors. The nowadays trend of ASIP design is focused on automatic simulator generation based on a processor description in an architecture description language. The simulator is used for testing and validation of designed processor or target application...
As communication networks move towards 40/100G transmission capacities, wire-speed packet processing is becoming much critical to implement. Most commercial solutions for the high-speed telecom market are based on either ASIC designs and/or network processors (NPs), while enterprise solutions can eventually make use of general purpose processors (GPPs) to deal with much slower processing requirements...
Current generations of high performance microprocessors feature multiple cores and micro-cores, with each supporting multiple threads implemented in hardware. Such designs routinely feature billions of transistors, and chip layout teams are frequently hard pressed for placement and routing of all the functional blocks and sub-blocks that go into the design. An additional complexity arises because...
In this paper, we present a low-power high-performance WiMAX chipset fully compliant with IEEE 802.16e specification corrigendum 1, 2 for mobile broad band access and WiMAX Forum System Profile Wave2. The chipset is comprised of a 632.7mW modem/router chip and a 364mW RF transceiver chip, both devel oped in 65nm CMOS. A fully programmable SIMD processor is used for WiMAX baseband and only parts of...
Reconfigurable Field Programmable Gate Arrays (FPGAs) are growing the attention of developers of mission- and safety-critical applications (e.g., aerospace ones), as they allow unprecedented levels of performance, which are making these devices particularly attractive as ASICs replacement, and as they offer the unique feature of in-the-field reconfiguration. However, the sensitivity of reconfigurable...
Artificial intelligence (Al) functions are becoming important in smartphones, portable game consoles, and robots for such intelligent applications as object detection, recognition, and human-computer interfaces (HCI). Most of these functions are realized in software with neural networks (NN) and fuzzy systems (FS), but due to power and speed limitations, a hardware solution is needed. For example,...
Due to the highly complicated control structures of modern processors as well as ASICs, some of the logical bugs may easily escape from the pre-silicon verification processes and remain into the silicon. Those bugs can only be found after the chip has been fabricated and used in the systems. So post-silicon debugging is becoming a essential part of the design flows for complicated and large system...
This paper describes an implantable microsystem being developed to continuously monitor intraocular pressure. The glass-in-silicon reflow process allows the formation of an embedded cavity and a variety of device shapes. A 0.18μm CMOS circuit fits within the cavity and uses vertical feedthroughs in the glass to interface with other components. An optical trigger wakes up the IC to take data, reducing...
This paper concerns the design and optimization of a digital hearing aid application. It aims to show that a suitably adapted ASIP can be constructed to create a highly optimized solution for the wide variety of complex algorithms that play a role in this domain. These algorithms are configurable to fit the various hearing impairments of different users. They pose significant challenges to digital...
Cairo University SPARC “CUSPARC” processor is an IP embedded processor core conforming to SPARC V8 ISA. CUSPARC is fully developed at Cairo University and is the first Egyptian processor. In this paper, the ASIC Implementation and Verification of the CUSPARC processor is described at 130nm technology node. CUSPARC scores a typical clock frequency of 260MHz, power dissipation of 0.11 mW/MHz and power...
This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into...
Processing structures based on arrays of computational elements form an important class of architectures, which includes field programmable gate arrays (FPGAs), systolic arrays, and various forms of multicore processors. A wide variety of design methods and tools have been targeted to regular processing arrays involving homogeneous processing elements. In this paper, we introduce the concept of field...
A flexible and efficient ECC processor is presented in this paper. We design an application-specific instruction set for the processor. The proposed parallel architecture ECC processor provides the lowest level finite-field operations and supports arbitrary elliptic curves and various ECC algorithms over general prime filed. Based on 130 nm standard-cell technology, the processor requires 184μs for...
Multimedia embedded systems require high performance specific computation to process the large among of data that characterizes the multimedia domain at low energy consumption due to battery life. Different optimizations at different levels can considerably improve performance and energy consumption and, after that, the address generation becomes the new performance bottleneck. This paper shows a...
This paper introduces a generation method of Application-domain Specific Instruction-set Processors (ASIP) and shows an design example. ASIP is a processor which has some extended instructions specific to application domain. First, advantage of ASIC is explained. Then, some processor generation approaches explained, and an ASIP development environment called ASIP Meister is introduced. Finally, design...
In this tutorial paper, we will outline a solution for prototyping, programming and implementing Application Specific Instruction-set Processors (ASIPs). A general introduction into this class of processor architectures and their characteristics is provided. The Synopsys Processor Designer tool suite and the LISA language for ASIP design are jointly introduced in the context of a H.264 design example...
Application-specific instruction set processors used in embedded systems are highly optimized for a given task. On this type of processors runs a specific application. Therefore, the designer should have a tool which helps him or her in the task of processor and application optimization. One of such tools is profiler. It can discover problematic parts, such as bottleneck points, in the processor and...
Embedded media applications have traditionally used custom ASICs to meet their real-time performance requirements. However, the combination of increasing chip design cost and availability of commodity many-core processors is making programmable devices increasingly attractive alternatives. Yet for these processors to be successful in this role, programming systems are needed that can automate the...
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