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In this paper, we proposed a new design of hybrid adder for area-efficient 32-bit floating point multiplier. By combining conventional ripple carry adder (RCA) and Wallace tree adder for adding Generated Partial Products (GPPs), the speed can be improved. Toom-3 multiplication method applied on 24×24 mantissa multiplier with a reduced complexity of (n1.465). Pre-determined Partial Products Generation...
Stochastic turbo decoder is a new scheme for turbo codes. But the long decoding latency and high complexity are two main challenges for fully parallel stochastic turbo decoders. In this paper, we proposed a novel stochastic turbo decoder scheme with two high accuracy stochastic operator modules, including no-scaling stochastic addition and stochastic normalization operator, which can improve the decoding...
In this paper, the high throughput hardware architecture is designed to calculate the Sum of Absolute Difference (SAD) based on the variable block size of the image. Even though the fixed block size motion estimation is simple with respect to the complexity of the variable block size motion estimation, variable block size estimation technique results in exquisite performance. Motion estimation is...
A radix-4 energy efficient carry-free truncated multiplier is proposed and designed based on a linear array left-to-right carry-free (LRCF) multiplier [1]-[3]. In our proposed multiplier, the final product is obtained in parallel with the reduction of partial products in carry-save form using an improved on-the-fly conversion of O(n) size based on conditional adders. In addition to the proposed multiplier,...
Check node processing dominates the complexity of nonbinary LDPC decoding. Trellis based min-max algorithm[1] can reduce the computation complexity and generate the message from check node to variable node in parallel. In this paper, power representation is used to implement check node processor, adder structures over GF(q) using power representation in trellis based check node processing are proposed...
Recently, polar codes have received much attention due to their simple structure and low decoding complexity. However, because of the long decoding latency, polar codes are still not suitable for real-time applications. In this paper, by the analysis of the position of frozen bits and the architecture of conventional SC decoder, we present an efficient SC decoder architecture. Using the proposed architecture,...
In this paper, we present and compare the design and the performances of ten different implementations for a 16-bit adder in a 180nm CMOS standard-cell technology. Ripple carry adder, increment adder, triangle adder, uniform and progressive carry select adder, uniform and progressive carry bypass adder, conditional adder, ripple carry look ahead adder and hierarchical carry look ahead adder are taken...
In this paper, we propose an area efficient adder based reverse converter for a recently proposed new moduli set {22n+1 − 1, 22n+1, 22n − 1}. First, we simplify the New Chinese Remainder Theorem (New CRT I) to obtain a reverse converter. Second, we further reduce the resulting architecture to obtain a memoryless reverse converter that uses three 2n bits CSAs (CSA1, CSA2, CSA3), two parallel CPAs (2n...
The pipelined architecture has gained popularity due to its ability to achieve high throughput and low hardware complexity, low power consumption. Thus, these architectures are widely used in many applications, mainly for the real-time applications. The fast Fourier transform (FFT) offers optimized design for the complex samples, i.e., complex valued FFT (CFFT) but not for the real input samples,...
Among various discrete transforms, discrete Fourier transformation (DFT) is the most important technique that performs Fourier analysis in various practical applications, such as digital signal processing, wireless communications, to name a few. Due to its ultra-high computing complexity as O(N2), in practice the N-point DFT is usually performed in the form of fast Fourier transformation (FFT) with...
In this paper the design of multipliers which is less complex and power consuming is made of basic electronic components such as gates and adders. This design lowers the complexity of the circuit and works on the basic principle of multiplication and less number of transistors. The results show the multiplier is less complex and works effectively in large multiplications.
At present scenario Polynomial basis multipliers are used because they are relatively simple to design, and offer scalability for the fields of higher orders. It is used in Cryptographic and FFT applications for secure data encryption and decryption which deals with discrete structure and mathematical arithmetic. Since it uses modular arithmetic operation, it is found that it has the latency of m...
Blum-Blum-Shub (x2 mod N) is proved cryptographically secure pseudorandom generator which passes all the statistical properties of randomness tests. It is secure, because it cannot predict in forward direction as well as in backward direction. The reason is hard to factorize the large integer N (≥ 264) which is the product of two special primes. The major challenge of BBS is the efficient...
This paper presents GF(2m) multiplier for trinomials. Multiplier is implemented using digit serial/parallel architecture. Architecture is constructed using modified LSD-first multiplication algorithm. Bit throughput is a critical factor of GF(2m) multiplication for different applications.Applications such as digital signal processors, computer systems, FIR filter implementation. This architecture...
The objective of the work is to design and compare high performance and energy efficient VLSI adders for the various bit-level up to 64-bit using advanced CMOS technology. To compare the performance of the adders, recent algorithms of Weinberger, Ling and Manchester carry chain are selected amongst the high performance adders. These three algorithms are chosen because their efficient architectures...
Polar codes are a class of codes discovered recently, which are proved to have capacity-achieving performance. The hardware implementations of successive cancellation (SC) decoding and List SC decoding are increasing dramatically now. However, throughput of these hardware structures remain to be improved on the one hand. On the other hand, stochastic computation is now wildly used because it uses...
Bit-interleaved coded modulation with iterative decoding has been widely adopted in modern wireless communication systems because of its spectral efficiency and low detection complexity. Because of the iterative decoding structure, the overall decoding latency depends on the latency of both the demapper and the channel decoder. In this work, a parallel demapper architecture is proposed for a low latency...
In this work efficient modulo 2n+1 fused multiply-add-add units for weighted and diminished-1 operands are proposed. The proposed architectures can be applied in systems in which fused multiply-add-add units accelerate the execution of the targeting algorithms. Long integer arithmetic would also show considerable gains by using multiply-add-add units. Also, implementation results for the proposed...
Finite Impulse Response (FIR) filters are widely used in multistandard wireless communications. The two key requirements of FIR filters are reconfigurabilty and low complexity. The researches have been introduced many architectures for above key metrics. For reconfigurable FIR filter, two architectures was implemented, namely Constant Shift Method [CSM] and Programmable Shift Method [PSM]. The complexity...
In 2004, Robert Jackson and Sunil Talwar published a novel method of decomposing binary prefix addition. Their work sought to balance the complexity of the generate and propagate terms that bear the computational load in parallel prefix adders. This paper presents an implementation of a 64-bit adder based on this method, as well as an improved method of expressing this complex decomposition. This...
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