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Due to their flexibility and high performance, Coarse Grained Reconfigurable Array (CGRA) are a topic of increasing research interest. However, CGRAs also have the potential to achieve very high energy efficiency in comparison to other reconfigurable architectures when hardware optimizations are applied. Some of these optimizations are common for more traditional processors but can also lead to large...
Reconfigurable Processor (RP) provides great flexibility of hardware re-configurability through software solution for high-performance computing. RP is used as a DSP in Samsung DTV and Camera to run the Audio, Video codecs and image quality enhancement algorithms. RP runs in two modes: VLIW (Very Large Instruction Word) and CGRA (Coarse Grain Reconfigurable Array). To minimize the time-to-market of...
This study presents a design of a distributed architecture and an application for automated demand response, in which one electricity aggregator cooperates with a group of consumers. The distributed architecture utilizes an asynchronous message oriented middleware to integrate the defined components. The application adopts a distributed demand response optimization algorithm for the validation of...
The IEEE 1687 Standard specifies an access network and a description language for embedded instruments. In this paper, we present an optimization technique to minimize the segment insertion bit (SIB) programming overhead for IEEE 1687-compliant access architectures. We first present an optimal solution based on dynamic programming for concurrent access schedules. This technique is then utilized to...
The recent push for electrified vehicles, including both plug-in hybrid vehicles and pure electric vehicle may further increase peak electrical load if left unmitigated, resulting in more demand for generation and transmission capacities. Fortunately, PEVs can be treated as controllable loads or even power sources under extraneous situations for demand side management (DSM). Although centralized approach...
Feature matching is a fundamental problem in many computer vision tasks. As datasets become larger, and individual image resolution increases, this is becoming more and more computationally demanding work. While prior knowledge about the scene geometry can, in some cases, reduce the number of image pairs that need to be considered, the sheer volume of data means that parallel and distributed computing...
One of the key issues for system level design topic is the design time. This paper describes custom processor design tool as part of C-to-hardware flow and analyses its design time. The flow starts with C code specification and ends with FPGA implementation. The way the C code is processed has impact on the flow execution time. The implemented C code processing results with Control Flow Graph (CFG),...
The paper presents an agent-based scheduling and energy management system for a smart distribution feeder which is installed on a test site and includes an electric car sharing fleet. Distributed Energy storage systems provide flexibility in the operation of the test site, where the integration of multiple power sources including Renewable Energy Sources and Distributed Generators is implemented....
This paper describes performance optimizations of a transfer controller for an FPGA-based blocked parallel matrix multiplication accelerator. One of the key challenges of the controller is the generation of a sequence of host memory addresses to transfer blocks of matrices between host and on-chip memories. These addresses are not contiguous, thereby introducing complexity for the controller design...
In this paper we address the mapping of mixed-criticality hard real-time applications on distributed embedded architectures. We assume that the architecture provides both spatial and temporal partitioning, thus enforcing enough separation between applications. With temporal partitioning, each application runs in a separate partition, and each partition is allocated several time slots on the processors...
In this paper we are interested in mixed-criticality embedded real-time applications mapped on distributed heterogeneous architectures. The architecture provides both spatial and temporal partitioning, thus enforcing enough separation for the critical applications. With temporal partitioning, each application is allowed to run only within predefined time slots, allocated on each processor. The sequence...
We introduce a method of partitioning for massively-parallel hardware accelerated functional verification. Our approach augments classical hypergraph partitioning to model temporal dependencies that maximize parallelization within the instruction memories of the machine. Simulation depth is further reduced by optimizing path criticality and cut directionality. Our techniques are demonstrated on an...
The emerging computational grid infrastructure consists of widely distributed heterogeneous resources, which makes mapping of increasingly complex applications a very challenging task. Utility Management Systems (UMS) manage large number of workflows with high resource requirements and thereby optimization of resource utilization has to be adapted. In this work we propose the architecture that implements...
To provide best scheduling solution for the Shenzhou 8 space mission, the scheduling algorithms and configurations are determined before actual mission platform developing using a tryout architecture in Beijing Aerospace Control Center. The architecture is designed agile and extendable so that various processes can be implemented to validate and optimize the algorithms rapidly. With this architecture,...
A distributed MAS (multi agent system) architecture for moveable port resource operation has been presented in the paper, which builds upon elements from decentralized strategies. The system provides a feasible optimization solution to the problem due to its inherent complexity. Under such solution, an intelligent planning algorithm is continuously optimized by the dynamic and co-operative rescheduling...
A design approach for multiprocessor systems on FPGAs is presented. The goal is to customize such systems for target parallel programs by simultaneously solving the problems of task mapping and high level synthesis. By considering the effect of fixed-priority preemptive scheduling when several tasks share a processor resource, a broad spectrum of embedded application requirements is covered. Experimental...
The challenges of deriving early-adopter competitive advantage, even with fabless access to process technology, through leveraging features offered by the advanced, and possibly disruptive, process technologies in real SoC products, are outlined. A structured methodology for addressing these challenges, and bridging the gap between process and design, sufficiently early in the development cycle to...
Multi-core SoC created great opportunities to increase overall system performance while keeping the power in check but also created many design challenges that designers must now overcome. The challenge of doubling performance every two years used to drive superscalar design with more functional units running concurrently or deeper pipeline racing for highest frequency at the cost of higher power...
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